Searched refs:JH7110_SYSCLK_AXI_CFG0 (Results 1 - 2 of 2) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h24 #define JH7110_SYSCLK_AXI_CFG0 7 macro
/src/sys/arch/riscv/starfive/
H A Djh7110_clkc.c55 #define JH7110_SYSCLK_AXI_CFG0 7 macro
432 JH71X0CLKC_DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, "bus_root"),

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