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    Searched refs:SecondReg (Results 1 - 5 of 5) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset,
2318 SecondReg = Op1->getOperand(0).getReg();
2319 if (FirstReg == SecondReg)
2421 Register FirstReg, SecondReg;
2429 FirstReg, SecondReg, BaseReg,
2437 MRI->constrainRegClass(SecondReg, TRC);
2443 .addReg(SecondReg, RegState::Define)
2457 .addReg(SecondReg)
2474 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg);
2475 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 4343 unsigned SecondReg = Inst.getOperand(1).getReg();
4359 FirstReg, SecondReg, IDLoc, STI);
4367 FirstReg, SecondReg, IDLoc, STI);
5285 unsigned SecondReg = nextReg(FirstReg);
5287 if (!SecondReg)
5306 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5308 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
5332 unsigned SecondReg = nextReg(FirstReg);
5334 if (!SecondReg)
5350 std::swap(FirstReg, SecondReg);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 6192 unsigned SecondReg;
6193 Res = tryParseScalarRegister(SecondReg);
6197 if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 ||
6198 (isXReg && !XRegClass.contains(SecondReg)) ||
6199 (isWReg && !WRegClass.contains(SecondReg))) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1633 SecondReg = SwapOps ? TrueReg : FalseReg;
1650 .addReg(FirstReg).addReg(SecondReg)
PPCISelLowering.cpp 6711 const unsigned SecondReg = State.AllocateReg(PPC::R10);
6712 assert(FirstReg && SecondReg &&
6717 CCValAssign::getCustomReg(ValNo, ValVT, SecondReg, RegVT, LocInfo));

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