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    Searched refs:Wd (Results 1 - 2 of 2) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 712 uint16_t Wd = im(2), Of = im(3);
713 assert(Wd <= W0);
714 if (Wd == 0)
718 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
719 RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
721 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
723 return rr0(eZXT(RC, Wd), Outputs);
724 return rr0(eSXT(RC, Wd), Outputs);
728 uint16_t Wd = im(3), Of = im(4)
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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEISelLowering.cpp 1823 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
3239 // insert_fw_pseudo $wd, $wd_in, $n, $fs
3242 // insve_w $wd[$n], $wd_in, $wt[0]
3249 Register Wd = MI.getOperand(0).getReg();
3261 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3273 // insert_fd_pseudo $wd, $fs, n
3276 // insve_d $wd[$n], $wd_in, $wt[0]
3285 Register Wd = MI.getOperand(0).getReg();
3295 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3305 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
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