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    Searched refs:getRegBitWidth (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonBitTracker.cpp 94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
271 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
311 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
346 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
355 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
369 uint16_t W1 = getRegBitWidth(Reg[1]);
698 uint16_t W1 = getRegBitWidth(Reg[1]);
753 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
765 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32)
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BitTracker.cpp 329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
350 uint16_t BW = getRegBitWidth(RR);
709 uint16_t W = getRegBitWidth(Reg);
733 uint16_t W = getRegBitWidth(RD);
747 uint16_t WD = getRegBitWidth(RD);
748 uint16_t WS = getRegBitWidth(RS);
805 uint16_t DefBW = ME.getRegBitWidth(DefRR);
883 uint16_t DefBW = ME.getRegBitWidth(RD);
BitTracker.h 397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
HexagonConstPropagation.cpp 1861 unsigned getRegBitWidth(unsigned Reg) const;
1998 unsigned W = getRegBitWidth(DefR.Reg);
2159 unsigned BW = getRegBitWidth(R1.Reg);
2366 unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const {
2704 unsigned W = getRegBitWidth(DefR.Reg);
2758 unsigned BW = getRegBitWidth(DefR.Reg);
2907 unsigned W = getRegBitWidth(R);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/
AMDGPUBaseInfo.h 769 unsigned getRegBitWidth(unsigned RCID);
772 unsigned getRegBitWidth(const MCRegisterClass &RC);
AMDGPUBaseInfo.cpp 1591 unsigned getRegBitWidth(unsigned RCID) {
1675 unsigned getRegBitWidth(const MCRegisterClass &RC) {
1676 return getRegBitWidth(RC.getID());
1683 return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
GCNHazardRecognizer.cpp 733 if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&
745 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256);
751 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64)
SIFoldOperands.cpp 915 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
919 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
SIRegisterInfo.cpp 1044 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8;
2223 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC);
SIInstrInfo.cpp 2505 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2520 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
AMDGPUInstPrinter.cpp 680 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));

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