| /xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/tests/ |
| H A D | test_glsl_to_tgsi_array_merge.cpp | 757 { TGSI_OPCODE_MOV , {MT(1, 1, WRITEMASK_XYZW)}, {MT(0, in0, "")}, {}, ARR()},
758 { TGSI_OPCODE_MOV , {MT(2, 1, WRITEMASK_XYZW)}, {MT(0, in1, "")}, {}, ARR()},
759 { TGSI_OPCODE_ADD , {MT(0,out0, WRITEMASK_XYZW)}, {MT(1,1,"xyzw"), MT(2,1,"xyzw")}, {}, ARR()},
769 { TGSI_OPCODE_MOV , {MT(1, 1, WRITEMASK_X)}, {MT(0, in0, "")}, {}, ARR()},
770 { TGSI_OPCODE_MOV , {MT(2, 1, WRITEMASK_Y)}, {MT(0, in1, "")}, {}, ARR()},
771 { TGSI_OPCODE_ADD , {MT(0,out0,1)}, {MT(1,1,"x"), MT(2,1,"y")}, {}, ARR()},
782 { TGSI_OPCODE_MOV, {MT(1, 1, WRITEMASK_X)}, {MT(0, in0, "")}, {}, ARR()},
784 { TGSI_OPCODE_ADD, {MT(0,1, WRITEMASK_X)}, {MT(1,1,"x"), {MT(0,1, "x")}}, {}, ARR()},
800 { TGSI_OPCODE_MOV, {MT(1, 1, WRITEMASK_Z)}, {MT(0, in0, "")}, {}, ARR()},
802 { TGSI_OPCODE_ADD, {MT(0,1, WRITEMASK_X)}, {MT(1,1,"z"), {MT(0,1, "x")}}, {}, ARR()},
[all...] |
| H A D | st_tests_common.h | 43 struct ARR {}; struct
61 const std::vector<std::tuple<int,int, const char*>>&_to, ARR with_array);
|
| H A D | st_tests_common.cpp | 117 ARR with_array):
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/tests/ |
| H A D | test_glsl_to_tgsi_array_merge.cpp | 757 { TGSI_OPCODE_MOV , {MT(1, 1, WRITEMASK_XYZW)}, {MT(0, in0, "")}, {}, ARR()},
758 { TGSI_OPCODE_MOV , {MT(2, 1, WRITEMASK_XYZW)}, {MT(0, in1, "")}, {}, ARR()},
759 { TGSI_OPCODE_ADD , {MT(0,out0, WRITEMASK_XYZW)}, {MT(1,1,"xyzw"), MT(2,1,"xyzw")}, {}, ARR()},
769 { TGSI_OPCODE_MOV , {MT(1, 1, WRITEMASK_X)}, {MT(0, in0, "")}, {}, ARR()},
770 { TGSI_OPCODE_MOV , {MT(2, 1, WRITEMASK_Y)}, {MT(0, in1, "")}, {}, ARR()},
771 { TGSI_OPCODE_ADD , {MT(0,out0,1)}, {MT(1,1,"x"), MT(2,1,"y")}, {}, ARR()},
782 { TGSI_OPCODE_MOV, {MT(1, 1, WRITEMASK_X)}, {MT(0, in0, "")}, {}, ARR()},
784 { TGSI_OPCODE_ADD, {MT(0,1, WRITEMASK_X)}, {MT(1,1,"x"), {MT(0,1, "x")}}, {}, ARR()},
800 { TGSI_OPCODE_MOV, {MT(1, 1, WRITEMASK_Z)}, {MT(0, in0, "")}, {}, ARR()},
802 { TGSI_OPCODE_ADD, {MT(0,1, WRITEMASK_X)}, {MT(1,1,"z"), {MT(0,1, "x")}}, {}, ARR()},
[all...] |
| H A D | st_tests_common.h | 43 struct ARR {}; struct
61 const std::vector<std::tuple<int,int, const char*>>&_to, ARR with_array);
|
| H A D | st_tests_common.cpp | 117 ARR with_array):
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/tests/graw/vertex-shader/ |
| H A D | vert-arr.sh | 20 ARR ADDR[0].x, TEMP[0]
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/tests/graw/vertex-shader/ |
| H A D | vert-arr.sh | 20 ARR ADDR[0].x, TEMP[0]
|
| /xsrc/external/mit/MesaLib/dist/src/compiler/glsl/tests/ |
| H A D | sampler_types_test.cpp | 40 #define T(TYPE, DIM, DATA_TYPE, ARR, SHAD, COMPS) \
47 ARR; \
|
| /xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/tests/ |
| H A D | sampler_types_test.cpp | 40 #define T(TYPE, DIM, DATA_TYPE, ARR, SHAD, COMPS) \
47 ARR; \
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 88 OP11(ARR)
|
| H A D | tgsi_info_opcodes.h | 62 OPCODE(1, 1, COMP, ARR)
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_opcode_tmp.h | 93 OP11(ARR)
|
| H A D | tgsi_info_opcodes.h | 62 OPCODE(1, 1, COMP, ARR)
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 7.10.rst | 159 - r600g: translate ARR instruction for evergreen
2009 - r600g: translate ARR instruction
|
| H A D | 19.1.0.rst | 4561 - tgsi_to_nir: Fix the TGSI ARR translation by converting the result to
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/ |
| H A D | tgsi.rst | 629 .. opcode:: ARR - Address Register Load With Round
|
| /xsrc/external/mit/MesaLib/dist/docs/gallium/ |
| H A D | tgsi.rst | 632 .. opcode:: ARR - Address Register Load With Round
|