Searched refs:BLENDFACT_INV_DST_ALPHA (Results 1 - 22 of 22) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_state.c138 return BLENDFACT_INV_DST_ALPHA;
H A Dintel_context.h407 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_state.c138 return BLENDFACT_INV_DST_ALPHA;
H A Dintel_context.h407 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_render.c60 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ONE},
66 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ZERO},
72 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_SRC_ALPHA},
74 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_INV_SRC_ALPHA},
106 else if (sblend == BLENDFACT_INV_DST_ALPHA)
117 else if (sblend == BLENDFACT_INV_DST_ALPHA)
H A Di915_reg.h253 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_state_inlines.h135 return BLENDFACT_INV_DST_ALPHA;
H A Di915_reg.h969 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
H A Di915_state_emit.c186 else if (srcRGB == BLENDFACT_INV_DST_ALPHA)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_inlines.h134 return BLENDFACT_INV_DST_ALPHA;
H A Di915_state.c109 else if (src == BLENDFACT_INV_DST_ALPHA)
117 else if (dst == BLENDFACT_INV_DST_ALPHA)
131 else if (src == BLENDFACT_INV_DST_ALPHA)
139 else if (dst == BLENDFACT_INV_DST_ALPHA)
H A Di915_reg.h935 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_render.c62 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ONE},
68 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ZERO},
74 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_SRC_ALPHA},
76 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_INV_SRC_ALPHA},
110 else if (sblend == BLENDFACT_INV_DST_ALPHA)
121 else if (sblend == BLENDFACT_INV_DST_ALPHA)
H A Di915_reg.h242 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_render.c62 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ONE},
68 {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ZERO},
74 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_SRC_ALPHA},
76 {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_INV_SRC_ALPHA},
110 else if (sblend == BLENDFACT_INV_DST_ALPHA)
121 else if (sblend == BLENDFACT_INV_DST_ALPHA)
H A Di915_reg.h242 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h242 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h242 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h245 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
H A Dgen3_render.c84 /* OverReverse */ {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ONE},
87 /* Out */ {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ZERO},
90 /* AtopReverse */ {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_SRC_ALPHA},
91 /* Xor */ {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_INV_SRC_ALPHA},
164 else if (sblend == BLENDFACT_INV_DST_ALPHA)
176 else if (sblend == BLENDFACT_INV_DST_ALPHA)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h245 #define BLENDFACT_INV_DST_ALPHA 0x08 macro
H A Dgen3_render.c84 /* OverReverse */ {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ONE},
87 /* Out */ {1, 0, BLENDFACT_INV_DST_ALPHA, BLENDFACT_ZERO},
90 /* AtopReverse */ {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_SRC_ALPHA},
91 /* Xor */ {1, 1, BLENDFACT_INV_DST_ALPHA, BLENDFACT_INV_SRC_ALPHA},
164 else if (sblend == BLENDFACT_INV_DST_ALPHA)
176 else if (sblend == BLENDFACT_INV_DST_ALPHA)

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