| /xsrc/external/mit/MesaLib/dist/src/intel/compiler/ |
| H A D | test_eu_compact.cpp | 44 case BRW_ALIGN_1:
236 CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 },
237 CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 },
238 CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 },
239 CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 },
240 CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 },
241 CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 },
242 CompactParams{ 110, BRW_ALIGN_1 },
243 CompactParams{ 120, BRW_ALIGN_1 },
244 CompactParams{ 125, BRW_ALIGN_1 }
[all...] |
| H A D | brw_vec4_generator.cpp | 68 brw_set_default_access_mode(p, BRW_ALIGN_1);
227 brw_set_default_access_mode(p, BRW_ALIGN_1);
305 brw_set_default_access_mode(p, BRW_ALIGN_1);
391 brw_set_default_access_mode(p, BRW_ALIGN_1);
438 brw_set_default_access_mode(p, BRW_ALIGN_1);
478 brw_set_default_access_mode(p, BRW_ALIGN_1);
536 brw_set_default_access_mode(p, BRW_ALIGN_1);
548 brw_set_default_access_mode(p, BRW_ALIGN_1);
566 brw_set_default_access_mode(p, BRW_ALIGN_1);
630 brw_set_default_access_mode(p, BRW_ALIGN_1);
[all...] |
| H A D | brw_clip_util.c | 96 brw_set_default_access_mode(p, BRW_ALIGN_1);
211 brw_set_default_access_mode(p, BRW_ALIGN_1);
232 brw_set_default_access_mode(p, BRW_ALIGN_1);
|
| H A D | brw_eu_emit.c | 146 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
169 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
283 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
291 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
298 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
399 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
405 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
827 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1133 brw_get_default_access_mode(p) == BRW_ALIGN_1 &&
1274 brw_set_default_access_mode(p, BRW_ALIGN_1);
[all...] |
| H A D | brw_disasm.c | 922 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
974 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1254 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1341 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1415 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1637 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1699 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1893 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
|
| H A D | brw_eu_validate.c | 317 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
850 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
896 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
1696 unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ?
1822 brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/ |
| H A D | brw_vec4_generator.cpp | 67 brw_set_default_access_mode(p, BRW_ALIGN_1);
230 brw_set_default_access_mode(p, BRW_ALIGN_1);
303 brw_set_default_access_mode(p, BRW_ALIGN_1);
389 brw_set_default_access_mode(p, BRW_ALIGN_1);
436 brw_set_default_access_mode(p, BRW_ALIGN_1);
478 brw_set_default_access_mode(p, BRW_ALIGN_1);
537 brw_set_default_access_mode(p, BRW_ALIGN_1);
549 brw_set_default_access_mode(p, BRW_ALIGN_1);
567 brw_set_default_access_mode(p, BRW_ALIGN_1);
631 brw_set_default_access_mode(p, BRW_ALIGN_1);
[all...] |
| H A D | brw_clip_util.c | 96 brw_set_default_access_mode(p, BRW_ALIGN_1);
211 brw_set_default_access_mode(p, BRW_ALIGN_1);
232 brw_set_default_access_mode(p, BRW_ALIGN_1);
|
| H A D | brw_eu_emit.c | 129 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
152 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
252 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
260 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
267 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
364 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
370 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
718 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1019 brw_get_default_access_mode(p) == BRW_ALIGN_1 &&
1160 brw_set_default_access_mode(p, BRW_ALIGN_1);
[all...] |
| H A D | brw_disasm.c | 760 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
811 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1080 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1164 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1232 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1418 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1479 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1592 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
|
| H A D | test_eu_compact.cpp | 297 brw_set_default_access_mode(p, BRW_ALIGN_1);
|
| H A D | brw_eu_validate.c | 763 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
809 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
1609 unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ?
1731 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
|
| H A D | brw_eu_defines.h | 95 #define BRW_ALIGN_1 0 macro
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/ |
| H A D | brw_disasm.c | 523 if (inst->header.access_mode == BRW_ALIGN_1) {
702 else if (inst->header.access_mode == BRW_ALIGN_1) {
751 else if (inst->header.access_mode == BRW_ALIGN_1) {
850 if (inst->header.access_mode == BRW_ALIGN_1)
|
| H A D | brw_eu_emit.c | 116 if (insn->header.access_mode == BRW_ALIGN_1) {
132 if (insn->header.access_mode == BRW_ALIGN_1) {
260 if (insn->header.access_mode == BRW_ALIGN_1) {
270 if (insn->header.access_mode == BRW_ALIGN_1) {
277 if (insn->header.access_mode == BRW_ALIGN_1) {
333 if (insn->header.access_mode == BRW_ALIGN_1) {
341 if (insn->header.access_mode == BRW_ALIGN_1) {
1649 brw_set_access_mode(p, BRW_ALIGN_1);
1697 brw_set_access_mode(p, BRW_ALIGN_1);
1878 brw_set_access_mode(p, BRW_ALIGN_1);
[all...] |
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/ |
| H A D | brw_disasm.c | 523 if (inst->header.access_mode == BRW_ALIGN_1) {
702 else if (inst->header.access_mode == BRW_ALIGN_1) {
751 else if (inst->header.access_mode == BRW_ALIGN_1) {
850 if (inst->header.access_mode == BRW_ALIGN_1)
|
| H A D | brw_eu_emit.c | 116 if (insn->header.access_mode == BRW_ALIGN_1) {
132 if (insn->header.access_mode == BRW_ALIGN_1) {
260 if (insn->header.access_mode == BRW_ALIGN_1) {
270 if (insn->header.access_mode == BRW_ALIGN_1) {
277 if (insn->header.access_mode == BRW_ALIGN_1) {
333 if (insn->header.access_mode == BRW_ALIGN_1) {
341 if (insn->header.access_mode == BRW_ALIGN_1) {
1649 brw_set_access_mode(p, BRW_ALIGN_1);
1697 brw_set_access_mode(p, BRW_ALIGN_1);
1878 brw_set_access_mode(p, BRW_ALIGN_1);
[all...] |
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| H A D | gen8_eu.c | 344 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
467 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
538 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| H A D | gen8_eu.c | 344 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
467 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
538 if (__gen8_access_mode(inst) == BRW_ALIGN_1) {
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| H A D | brw_ff_gs_emit.c | 451 brw_set_default_access_mode(p, BRW_ALIGN_1);
|
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| H A D | brw_defines.h | 512 #define BRW_ALIGN_1 0 macro
|
| /xsrc/external/mit/xf86-video-intel/dist/xvmc/ |
| H A D | brw_defines.h | 512 #define BRW_ALIGN_1 0 macro
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| H A D | brw_defines.h | 512 #define BRW_ALIGN_1 0 macro
|
| /xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/ |
| H A D | brw_defines.h | 512 #define BRW_ALIGN_1 0 macro
|
| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| H A D | brw_defines.h | 505 #define BRW_ALIGN_1 0 macro
|