Searched refs:BRW_BLENDFACTOR_COUNT (Results 1 - 3 of 3) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_render.c92 #define BRW_BLENDFACTOR_COUNT (BRW_BLENDFACTOR_INV_DST_ALPHA + 1) macro
733 brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT][BRW_BLENDFACTOR_COUNT];
1246 for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
1247 for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
2522 BRW_BLENDFACTOR_COUNT * BRW_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE,
2530 for (src = 0; src < BRW_BLENDFACTOR_COUNT; src++) {
2531 for (dst = 0; dst < BRW_BLENDFACTOR_COUNT; dst++) {
2532 uint32_t blend_state_offset = (src * BRW_BLENDFACTOR_COUNT
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_render.c92 #define BRW_BLENDFACTOR_COUNT (BRW_BLENDFACTOR_INV_DST_ALPHA + 1) macro
733 brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT][BRW_BLENDFACTOR_COUNT];
1246 for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
1247 for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
2522 BRW_BLENDFACTOR_COUNT * BRW_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE,
2530 for (src = 0; src < BRW_BLENDFACTOR_COUNT; src++) {
2531 for (dst = 0; dst < BRW_BLENDFACTOR_COUNT; dst++) {
2532 uint32_t blend_state_offset = (src * BRW_BLENDFACTOR_COUNT
[all...]
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_render.c104 #define BRW_BLENDFACTOR_COUNT (BRW_BLENDFACTOR_INV_DST_ALPHA + 1) macro
574 brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
575 [BRW_BLENDFACTOR_COUNT];
972 for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
973 for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {

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