Searched refs:BRW_PIPE_CONTROL_IS_FLUSH (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_3d.c41 OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
H A Di965_reg.h333 #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) macro
H A Di965_video.c947 pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_3d.c41 OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH |
H A Di965_reg.h333 #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) macro
H A Di965_video.c948 pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h306 #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h306 #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c838 pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
H A Di810_reg.h2655 #define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) macro
H A Di965_render.c1217 pipe_ctrl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;

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