Searched refs:BRW_SURFACEFORMAT_R32G32_FLOAT (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di965_video.c922 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
931 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
942 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
952 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1308 src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1335 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1353 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Dbrw_defines.h325 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_video.c1022 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1034 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1048 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1061 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1557 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1566 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1455 src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1479 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1496 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2777 src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
2796 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2805 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Dbrw_defines.h325 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_video.c1023 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1035 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1049 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1062 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1558 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1567 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Di965_render.c1455 src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
1479 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1496 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2777 src_format = BRW_SURFACEFORMAT_R32G32_FLOAT;
2796 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
2805 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
H A Dbrw_defines.h325 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_defines.h325 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_defines.h325 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 macro

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