Searched refs:CACHE_MODE_0 (Results 1 - 9 of 9) sorted by relevance
| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| H A D | genX_state.c | 66 /* Before changing the value of CACHE_MODE_0 register, GFX pipeline must
80 /* Write to CACHE_MODE_0 (0x7000) */
82 anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
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| H A D | gen8_cmd_buffer.c | 131 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| H A D | i830_debug.c | 640 DEFINEREG(CACHE_MODE_0),
2391 ErrorF("cache_mode: 0x%08x/0x%08x\n", INREG(CACHE_MODE_0),
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| H A D | i810_reg.h | 431 #define CACHE_MODE_0 0x2120 macro
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| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| H A D | genX_state.c | 245 anv_batch_write_reg(&batch, GENX(CACHE_MODE_0), cm0) {
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| H A D | gfx8_cmd_buffer.c | 164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
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| /xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/ |
| H A D | i810_reg.h | 431 #define CACHE_MODE_0 0x2120 macro
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/ |
| H A D | i810_reg.h | 431 #define CACHE_MODE_0 0x2120 macro
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| H A D | iris_state.c | 1040 iris_emit_reg(batch, GENX(CACHE_MODE_0), reg) {
1550 * - Gfx9 Stencil PMA Fix: CACHE_MODE_0::STC PMA Optimization Enable
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