Searched refs:CMD_STATE_BASE_ADDRESS (Results 1 - 13 of 13) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_misc_state.c52 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
709 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
746 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
784 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
795 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
H A Dbrw_defines.h466 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_misc_state.c52 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
798 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (pkt_len - 2));
835 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
873 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2));
884 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
H A Dbrw_defines.h466 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dbrw_defines.h823 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Dbrw_defines.h823 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dbrw_defines.h823 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Dbrw_defines.h823 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Dbrw_defines.h816 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen4_render.h988 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
H A Dgen5_render.h1076 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen4_render.h988 #define CMD_STATE_BASE_ADDRESS 0x6101 macro
H A Dgen5_render.h1076 #define CMD_STATE_BASE_ADDRESS 0x6101 macro

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