Searched refs:CS (Results 1 - 25 of 67) sorted by relevance

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/xsrc/external/mit/xf86-video-sis/dist/src/
H A Dsis_cursor.h35 #define CS(x) (0x8500 + (x << 2)) macro
46 SIS_MMIO_IN32(pSiS->IOBase, CS(0)) & 0x40000000;
51 temp = SIS_MMIO_IN32(pSiS->IOBase, CS(0)); \
54 SIS_MMIO_OUT32(pSiS->IOBase, CS(0), temp); \
60 temp = SIS_MMIO_IN32(pSiS->IOBase, CS(0)); \
63 SIS_MMIO_OUT32(pSiS->IOBase, CS(0), temp); \
69 temp = SIS_MMIO_IN32(pSiS->IOBase, CS(0)); \
71 SIS_MMIO_OUT32(pSiS->IOBase, CS(0), temp); \
77 temp = SIS_MMIO_IN32(pSiS->IOBase, CS(0)); \
80 SIS_MMIO_OUT32(pSiS->IOBase, CS(
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/xsrc/external/mit/xorg-server/dist/hw/xfree86/x86emu/x86emu/
H A Dx86emui.h77 # if defined(__sun) && defined(CS)
78 # undef CS
H A Dregs.h114 * CS, DS, ES, SS.
117 #if defined(__sun) && defined(CS) /* avoid conflicts with Solaris sys/regset.h */
118 # undef CS
127 u16 CS, DS, SS, ES, FS, GS; member in struct:i386_segment_regs
169 #define R_CS seg.CS
270 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_urb.c43 #define CS 4 macro
91 } limits[CS+1] = {
121 if (csize < limits[CS].min_entry_size)
122 csize = limits[CS].min_entry_size;
146 brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
175 brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
199 "URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_urb.c43 #define CS 4 macro
91 } limits[CS+1] = {
121 if (csize < limits[CS].min_entry_size)
122 csize = limits[CS].min_entry_size;
146 brw->urb.nr_cs_entries = limits[CS].preferred_nr_entries;
175 brw->urb.nr_cs_entries = limits[CS].min_nr_entries;
199 "URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.0.2.rst102 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
103 - anv: Use a proper end-of-pipe sync instead of just CS stall
104 - anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stall
H A D13.0.2.rst115 - anv/cmd_buffer: Emit a CS stall before setting a CS pipeline
H A D19.3.5.rst118 - v3d: Sync on last CS when non-compute stage uses resource written by
119 CS
H A D20.0.1.rst121 - v3d: Sync on last CS when non-compute stage uses resource written by
122 CS
H A D9.2.3.rst60 - i965: CS writes/reads should use I915_GEM_INSTRUCTION
H A D10.2.6.rst92 - radeon,r200: fix buffer validation after CS flush
H A D10.2.8.rst91 - r600g,radeonsi: make sure there's enough CS space before resuming
H A D10.3.2.rst41 the HDP cache before submitting a CS to the GPU
H A D12.0.5.rst69 - anv/cmd_buffer: Enable a CS stall workaround for Sky Lake gt4
H A D17.3.8.rst89 - i965: Hard code CS scratch_ids_per_subslice for Cherryview
H A D18.0.4.rst77 - i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
H A D19.0.6.rst112 - radv: allocate more space in the CS when emitting events
H A D11.1.2.rst145 - radeonsi: add DCC buffer for sampler views on new CS
H A D13.0.1.rst118 - anv/cmd_buffer: Enable a CS stall workaround for Sky Lake gt4
H A D13.0.3.rst84 - anv/cmd_buffer: Re-emit MEDIA_CURBE_LOAD when CS push constants are
H A D19.1.2.rst88 - vl: Use CS composite shader only if TEX_LZ and DIV are supported
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/x86emu/x86emu/
H A Dregs.h112 * CS, DS, ES, SS.
116 u16 CS, DS, SS, ES, FS, GS; member in struct:i386_segment_regs
166 #define R_CS seg.CS
267 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
/xsrc/external/mit/xf86-video-xgi/dist/src/
H A Dxgi_accel.h170 #define GuardBand(CS)\
176 if( lTemp < (CS) )\
184 if( lTemp >= (CS) ) break ;\
190 }while(lTemp < (CS)) ;\
194 #define GuardBand(CS)\
201 if( ((lTemp & pXGI->cmdQueueSizeMask ) < (BandSize + CS)) && ( r_port != w_port ) ) \
209 if( (lTemp & pXGI->cmdQueueSizeMask ) >= (BandSize + CS) ) \
218 #define GuardBand(CS)\
228 if( (lTemp & pXGI->cmdQueueSizeMask ) >= (BandSize + CS) ) \
H A Dxgi_cursor.h35 #define CS(x) (0x8500 + (x << 2)) macro
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md130 * CS = Compute Shader
141 * CS = Compute Shader
212 * Note that the SW CS always runs on the HW CS stage on all HW generations.
214 | GFX6-10 HW stage | CS | ACO terminology |
216 | SW stage | CS | `compute_cs` |

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