Searched refs:ChipConfig (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/xf86-video-glint/dist/src/
H A Dpm_dac.c92 pReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig) & 0xFFFFFFFD;
217 glintReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig);
231 RESTOREREG(ChipConfig);
H A Dpm2_dac.c167 pReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig) & 0xFFFFFFDD;
259 glintReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig);
332 GLINT_SLOW_WRITE_REG(glintReg->glintRegs[ChipConfig >> 3], ChipConfig);
H A Dpm2v_dac.c216 pReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig) & 0xFFFFFFDD;
287 glintReg->glintRegs[ChipConfig >> 3] = GLINT_READ_REG(ChipConfig);
351 GLINT_SLOW_WRITE_REG(glintReg->glintRegs[ChipConfig >> 3], ChipConfig);
H A Dpm3_dac.c550 STOREREG(ChipConfig, GLINT_READ_REG(ChipConfig) & 0xFFFFFFFD);
666 SAVEREG(ChipConfig);
736 RESTOREREG(ChipConfig);
H A Dglint_regs.h139 #define ChipConfig 0x0070 macro
/xsrc/external/mit/xf86-video-ag10e/dist/src/
H A Dglint_regs.h136 #define ChipConfig 0x0070 macro

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