Searched refs:Ctx (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di830_state.c64 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
67 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
69 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE |
85 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
86 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
193 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
194 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
214 i830->state.Ctx[I830_CTXREG_STATE2] &= ~ALPHA_TEST_REF_MASK;
215 i830->state.Ctx[I830_CTXREG_STATE
[all...]
H A Di915_state.c99 GLuint dw = i915->state.Ctx[reg]; \
102 dirty |= dw != i915->state.Ctx[reg]; \
103 i915->state.Ctx[reg] = dw; \
189 dw = i915->state.Ctx[I915_CTXREG_LIS6];
193 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
194 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
211 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
212 dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
228 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
229 dw1 != i915->state.Ctx[I915_CTXREG_LIS
[all...]
H A Di830_vtbl.c179 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
180 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
181 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
196 i830->state.Ctx[I830_CTXREG_VF] = v0;
197 i830->state.Ctx[I830_CTXREG_VF2] = v2;
198 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
241 int vft0 = i830->state.Ctx[I830_CTXREG_VF];
242 int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
392 sz += sizeof(state->Ctx);
487 emit(intel, state->Ctx, sizeo
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H A Di915_vtbl.c105 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
106 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
252 sz += sizeof(state->Ctx);
371 emit(intel, state->Ctx, sizeof(state->Ctx));
678 uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
683 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
685 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
H A Di830_context.h119 GLuint Ctx[I830_CTX_SETUP_SIZE]; member in struct:i830_hw_state
H A Di915_fragprog.c1240 GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
1313 if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
1314 s3 != i915->state.Ctx[I915_CTXREG_LIS3] ||
1315 s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
1332 i915->state.Ctx[I915_CTXREG_LIS2] = s2;
1333 i915->state.Ctx[I915_CTXREG_LIS3] = s3;
1334 i915->state.Ctx[I915_CTXREG_LIS4] = s4;
H A Di915_context.h215 GLuint Ctx[I915_CTX_SETUP_SIZE]; member in struct:i915_hw_state
H A Dintel_tris.c298 OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
300 (i830->state.Ctx[I830_CTXREG_VF2] << 16) |
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di830_state.c64 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
67 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
69 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE |
85 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
86 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
193 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
194 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
214 i830->state.Ctx[I830_CTXREG_STATE2] &= ~ALPHA_TEST_REF_MASK;
215 i830->state.Ctx[I830_CTXREG_STATE
[all...]
H A Di915_state.c99 GLuint dw = i915->state.Ctx[reg]; \
102 dirty |= dw != i915->state.Ctx[reg]; \
103 i915->state.Ctx[reg] = dw; \
189 dw = i915->state.Ctx[I915_CTXREG_LIS6];
193 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
194 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
211 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
212 dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
228 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
229 dw1 != i915->state.Ctx[I915_CTXREG_LIS
[all...]
H A Di830_vtbl.c179 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
180 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
181 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
196 i830->state.Ctx[I830_CTXREG_VF] = v0;
197 i830->state.Ctx[I830_CTXREG_VF2] = v2;
198 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
241 int vft0 = i830->state.Ctx[I830_CTXREG_VF];
242 int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
392 sz += sizeof(state->Ctx);
487 emit(intel, state->Ctx, sizeo
[all...]
H A Di915_vtbl.c104 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
105 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
251 sz += sizeof(state->Ctx);
370 emit(intel, state->Ctx, sizeof(state->Ctx));
677 uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
682 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
684 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
H A Di830_context.h119 GLuint Ctx[I830_CTX_SETUP_SIZE]; member in struct:i830_hw_state
H A Di915_fragprog.c1240 GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
1313 if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
1314 s3 != i915->state.Ctx[I915_CTXREG_LIS3] ||
1315 s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
1332 i915->state.Ctx[I915_CTXREG_LIS2] = s2;
1333 i915->state.Ctx[I915_CTXREG_LIS3] = s3;
1334 i915->state.Ctx[I915_CTXREG_LIS4] = s4;
H A Di915_context.h215 GLuint Ctx[I915_CTX_SETUP_SIZE]; member in struct:i915_hw_state
H A Dintel_tris.c298 OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
300 (i830->state.Ctx[I830_CTXREG_VF2] << 16) |
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_insert_NOPs.cpp820 template <typename Ctx>
821 using HandleInstr = void (*)(State& state, Ctx&, aco_ptr<Instruction>&,
824 template <typename Ctx, HandleInstr<Ctx> Handle>
826 handle_block(Program* program, Ctx& ctx, Block& block)
845 template <typename Ctx, HandleInstr<Ctx> Handle>
849 std::vector<Ctx> all_ctx(program->blocks.size());
854 Ctx& ctx = all_ctx[i];
861 Ctx loop_block_ct
[all...]
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Dbufferobj.c523 if (shared_binding || ctx != oldObj->Ctx) {
528 } else if (ctx == oldObj->Ctx) {
540 if (shared_binding || ctx != bufObj->Ctx)
542 else if (ctx == bufObj->Ctx)
931 assert(buf->Ctx == ctx);
936 buf->Ctx = NULL;
964 if (buf->Ctx == ctx) {
987 if (buf->Ctx == ctx) {
994 buf->Ctx = NULL;
1060 buf->Ctx
[all...]
H A Dmtypes.h1396 struct gl_context *Ctx; member in struct:gl_buffer_object
1397 GLint CtxRefCount; /**< Non-atomic references held by Ctx. */

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