Searched refs:DC3_DISPLAY_CFG (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vg.c712 dcfg = READ_REG32(DC3_DISPLAY_CFG);
714 WRITE_REG32(DC3_DISPLAY_CFG, dcfg);
1030 WRITE_REG32(DC3_DISPLAY_CFG, dcfg);
1078 dcfg = READ_REG32(DC3_DISPLAY_CFG) & ~(DC3_DCFG_DISP_MODE_MASK |
1083 WRITE_REG32(DC3_DISPLAY_CFG, dcfg);
1393 if (READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
1428 temp = READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_DISP_MODE_MASK;
1442 temp = READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_16BPP_MODE_MASK;
2281 dcfg = READ_REG32(DC3_DISPLAY_CFG);
2284 WRITE_REG32(DC3_DISPLAY_CFG, dcf
[all...]
H A Dcim_df.c696 if (READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
827 dcfg = READ_REG32(DC3_DISPLAY_CFG) & ~DC3_DCFG_VFHPEL_MASK;
834 WRITE_REG32(DC3_DISPLAY_CFG, dcfg | (fifo << 16));
1632 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
1735 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
1819 if (READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
1834 if (READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_DCEN)
2028 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
H A Dcim_vop.c542 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN))
577 if (!(READ_REG32(DC3_DISPLAY_CFG) & DC3_DCFG_TGEN) ||
H A Dcim_regs.h291 #define DC3_DISPLAY_CFG 0x00000008 macro
400 /* DC3_DISPLAY_CFG BIT FIELDS */

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