Searched refs:DC3_DV_CTL (Results 1 - 2 of 2) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vg.c862 temp = READ_REG32(DC3_DV_CTL);
864 WRITE_REG32(DC3_DV_CTL, (temp & ~DC3_DV_LINE_SIZE_MASK) | dv_size);
2241 temp = READ_REG32(DC3_DV_CTL);
2242 WRITE_REG32(DC3_DV_CTL,
2364 temp = READ_REG32(DC3_DV_CTL);
2365 WRITE_REG32(DC3_DV_CTL, temp | 0x00000001);
2619 vg_state->dv_ctl = READ_REG32(DC3_DV_CTL);
2779 WRITE_REG32(DC3_DV_CTL, vg_state->dv_ctl | 0x00000001);
H A Dcim_regs.h325 #define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ macro
538 /* DC3_DV_CTL BIT DEFINITIONS */

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