Searched refs:DC3_GENLK_CTL (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vip.c675 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
709 WRITE_REG32(DC3_GENLK_CTL, genlk_ctl);
729 temp = READ_REG32(DC3_GENLK_CTL);
737 WRITE_REG32(DC3_GENLK_CTL, temp);
1109 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_GENLK_ACTIVE)
1124 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_VIP_VID_OK)
1387 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
1422 if (READ_REG32(DC3_GENLK_CTL) & DC3_GC_GENLOCK_ENABLE)
H A Dcim_vg.c672 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
673 WRITE_REG32(DC3_GENLK_CTL, (genlk_ctl & ~DC3_GC_GENLOCK_ENABLE));
766 genlk_ctl = READ_REG32(DC3_GENLK_CTL) & ~(DC3_GC_ALPHA_FLICK_ENABLE |
787 WRITE_REG32(DC3_GENLK_CTL, genlk_ctl);
1370 genlk = READ_REG32(DC3_GENLK_CTL);
1656 genlk_ctl = READ_REG32(DC3_GENLK_CTL) & ~(DC3_GC_FLICKER_FILTER_MASK |
1663 WRITE_REG32(DC3_GENLK_CTL, genlk_ctl);
2633 vg_state->genlk_ctl = READ_REG32(DC3_GENLK_CTL);
2793 WRITE_REG32(DC3_GENLK_CTL, vg_state->genlk_ctl);
3508 genlk_ctl = READ_REG32(DC3_GENLK_CTL);
[all...]
H A Dcim_regs.h346 #define DC3_GENLK_CTL 0x000000D4 macro
606 /* DC3_GENLK_CTL DEFINITIONS */
H A Dcim_df.c599 if ((READ_REG32(DC3_GENLK_CTL) & DC3_GC_FLICKER_FILTER_ENABLE) ||

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