Searched refs:DC3_H_SYNC_TIMING (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_df.c474 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1092 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1292 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1712 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1714 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
2178 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
2456 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
2568 hsyncend = ((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1;
H A Dcim_vop.c66 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
455 hsyncstart = (READ_REG32(DC3_H_SYNC_TIMING) & 0xFFF) + 1;
H A Dcim_vg.c987 WRITE_REG32(DC3_H_SYNC_TIMING, temp);
1326 sync = READ_REG32(DC3_H_SYNC_TIMING);
2610 vg_state->h_sync = READ_REG32(DC3_H_SYNC_TIMING);
2770 WRITE_REG32(DC3_H_SYNC_TIMING, vg_state->h_sync);
H A Dcim_regs.h307 #define DC3_H_SYNC_TIMING 0x00000048 macro
499 /* DC3_H_SYNC_TIMING BIT FIELDS */

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