Searched refs:DC3_V_SYNC_TIMING (Results 1 - 3 of 3) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_df.c475 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1093 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1293 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1726 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
1728 vsyncstart = (READ_REG32(DC3_V_SYNC_TIMING) & 0xFFF) + 1;
2190 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
2464 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
2569 vsyncend = ((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1;
H A Dcim_vg.c930 temp -= (READ_REG32(DC3_V_SYNC_TIMING) & 0x7FF) + 1;
953 temp -= (READ_REG32(DC3_V_SYNC_TIMING) & 0x7FF) + 1;
994 WRITE_REG32(DC3_V_SYNC_TIMING, temp);
1340 sync = READ_REG32(DC3_V_SYNC_TIMING);
2613 vg_state->v_sync = READ_REG32(DC3_V_SYNC_TIMING);
2773 WRITE_REG32(DC3_V_SYNC_TIMING, vg_state->v_sync);
H A Dcim_regs.h310 #define DC3_V_SYNC_TIMING 0x00000058 macro
514 /* DC3_V_SYNC_TIMING BIT FIELDS */

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