Searched refs:DISPATCH_MODE_SIMD8 (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_tcs.cpp472 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_compiler.h1004 DISPATCH_MODE_SIMD8 = 3, enumerator in enum:shader_dispatch_mode
H A Dbrw_vec4_gs_visitor.cpp855 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_shader.cpp1332 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_vec4.cpp2962 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_pipeline.c1333 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
1489 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
1493 assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_gs_visitor.cpp826 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_compiler.h1241 DISPATCH_MODE_SIMD8 = 3, enumerator in enum:shader_dispatch_mode
H A Dbrw_shader.cpp1434 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
H A Dbrw_vec4.cpp2987 prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_pipeline.c1779 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
1966 tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ?
1970 assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_genX_exec.h621 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
640 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c2149 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
2152 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
2218 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
4146 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
4156 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_state_upload.c2132 assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
2135 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
2201 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
4073 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
4083 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h686 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
705 vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_state.c6799 vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8;
7033 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8)
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_state.c3701 gs.DispatchMode = DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_state.c4473 gs.DispatchMode = DISPATCH_MODE_SIMD8;
/xsrc/external/mit/MesaLib.old/src/intel/genxml/
H A Dgen10_pack.h4392 #define DISPATCH_MODE_SIMD8 3 macro
H A Dgen11_pack.h4503 #define DISPATCH_MODE_SIMD8 3 macro
H A Dgen8_pack.h3220 #define DISPATCH_MODE_SIMD8 3 macro
H A Dgen9_pack.h4345 #define DISPATCH_MODE_SIMD8 3 macro
/xsrc/external/mit/MesaLib/src/intel/genxml/
H A Dgen10_pack.h4392 #define DISPATCH_MODE_SIMD8 3 macro
H A Dgen11_pack.h4945 #define DISPATCH_MODE_SIMD8 3 macro
H A Dgen8_pack.h3236 #define DISPATCH_MODE_SIMD8 3 macro

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