Searched refs:FLUSH (Results 1 - 25 of 31) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/v3d/
H A Dv3dx_job.c39 cl_packet_length(FLUSH));
53 /* We just FLUSH here to tell the HW to cap the bin CLs with a
58 cl_emit(&job->bcl, FLUSH, flush);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/v3d/
H A Dv3dx_job.c40 cl_packet_length(FLUSH));
68 /* We just FLUSH here to tell the HW to cap the bin CLs with a
73 cl_emit(&job->bcl, FLUSH, flush);
/xsrc/external/mit/freetype/dist/src/gzip/
H A Dinfutil.h81 #define FLUSH {UPDOUT r=inflate_flush(s,z,r); LOADOUT} macro
82 #define NEEDOUT {if(m==0){WRAP if(m==0){FLUSH WRAP if(m==0) LEAVE}}r=Z_OK;}
H A Dinfcodes.c227 FLUSH
H A Dinfblock.c359 FLUSH
/xsrc/external/mit/MesaLib.old/dist/src/mesa/tnl_dd/
H A Dt_dd_dmatmp.h144 FLUSH();
195 FLUSH();
257 FLUSH();
286 FLUSH();
318 FLUSH();
342 FLUSH();
360 FLUSH();
/xsrc/external/mit/MesaLib/dist/src/mesa/tnl_dd/
H A Dt_dd_dmatmp.h144 FLUSH();
195 FLUSH();
257 FLUSH();
286 FLUSH();
318 FLUSH();
342 FLUSH();
360 FLUSH();
/xsrc/external/mit/xorg-server.old/dist/Xi/
H A Dxichangehierarchy.c445 FLUSH, enumerator in enum:ProcXIChangeHierarchy::__anon2e64b0800103
500 changes = FLUSH;
511 changes = FLUSH;
540 if (changes == FLUSH) {
/xsrc/external/mit/xorg-server/dist/Xi/
H A Dxichangehierarchy.c444 FLUSH, enumerator in enum:ProcXIChangeHierarchy::__anon5dcfde130103
496 changes = FLUSH;
507 changes = FLUSH;
536 if (changes == FLUSH) {
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_compute.c244 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
418 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
459 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
H A Dnve4_compute.c189 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
254 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
355 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
419 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
541 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
575 // there is no need to do FLUSH(NVE4_COMPUTE_FLUSH_CB) because
H A Dnvc0_shader_state.c250 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
H A Dnvc0_program.c876 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(FLUSH), 1);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_compute.c244 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
418 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
459 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
H A Dnve4_compute.c213 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
278 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
379 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
443 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
565 BEGIN_NVC0(push, NVE4_CP(FLUSH), 1);
620 // there is no need to do FLUSH(NVE4_COMPUTE_FLUSH_CB) because
H A Dnvc0_shader_state.c275 BEGIN_NVC0(push, NVC0_CP(FLUSH), 1);
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/xvmc/
H A DI810XvMC.h335 #define FLUSH(c) drmCommandNone(c->fd, DRM_I810_FLUSH) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/xvmc/
H A DI810XvMC.h335 #define FLUSH(c) drmCommandNone(c->fd, DRM_I810_FLUSH) macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A DI810XvMC.h335 #define FLUSH(c) drmCommandNone(c->fd, DRM_I810_FLUSH) macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_render.c152 #define FLUSH() INTEL_FIREVERTICES(intel) macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_render.c151 #define FLUSH() INTEL_FIREVERTICES(intel) macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/
H A Dfreedreno_batch.c530 if (FD_DBG(FLUSH)) {
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_job.c391 * until the FLUSH completes.
395 /* The FLUSH caps all of our bin lists with a
398 cl_emit(&job->bcl, FLUSH, flush);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_job.c391 * until the FLUSH completes.
395 /* The FLUSH caps all of our bin lists with a
398 cl_emit(&job->bcl, FLUSH, flush);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_swtcl.c393 #define FLUSH() RADEON_NEWPRIM( rmesa ) macro

Completed in 23 milliseconds

12