Searched refs:GEN6_3DSTATE_WM_DISPATCH_ENABLE (Results 1 - 14 of 14) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di965_reg.h139 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Di965_video.c1539 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
H A Di965_render.c2686 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di965_reg.h112 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di965_reg.h139 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Di965_video.c1540 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
H A Di965_render.c2686 GEN6_3DSTATE_WM_DISPATCH_ENABLE |
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di965_reg.h112 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen6_render.h105 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
394 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Dgen5_render.h138 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Dgen6_render.c730 GEN6_3DSTATE_WM_DISPATCH_ENABLE);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen6_render.h105 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
394 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Dgen5_render.h138 # define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) macro
H A Dgen6_render.c696 GEN6_3DSTATE_WM_DISPATCH_ENABLE);

Completed in 54 milliseconds