Searched refs:GEN6_COMPRESSION_1Q (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu.c95 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
H A Dbrw_eu.h85 #define GEN6_COMPRESSION_1Q 0 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu.c95 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
H A Dbrw_eu.h85 #define GEN6_COMPRESSION_1Q 0 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_eu.c874 case BRW_COMPRESSION_NONE: v = GEN6_COMPRESSION_1Q; break;
931 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
1063 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
1155 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_eu.c874 case BRW_COMPRESSION_NONE: v = GEN6_COMPRESSION_1Q; break;
931 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
1063 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
1155 __gen8_set_cmpt_control(insn, GEN6_COMPRESSION_1Q);
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_eu_defines.h112 #define GEN6_COMPRESSION_1Q 0 macro

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