Searched refs:GEN6_PIPE_CONTROL_CS_STALL (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen6_render.h448 #define GEN6_PIPE_CONTROL_CS_STALL (1 << 20) macro
H A Dgen6_render.c444 GEN6_PIPE_CONTROL_CS_STALL);
456 stall = GEN6_PIPE_CONTROL_CS_STALL;
468 OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL |
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen6_render.h448 #define GEN6_PIPE_CONTROL_CS_STALL (1 << 20) macro
H A Dgen6_render.c410 GEN6_PIPE_CONTROL_CS_STALL);
422 stall = GEN6_PIPE_CONTROL_CS_STALL;
434 OUT_BATCH(GEN6_PIPE_CONTROL_CS_STALL |

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