Searched refs:GENX (Results 1 - 25 of 71) sorted by relevance

123

/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/genxml/
H A Dgen_macros.h30 * The macro GENX() automatically suffixes whatever you give it with _vX
82 # define GENX(X) X##_v4 macro
85 # define GENX(X) X##_v5 macro
88 # define GENX(X) X##_v6 macro
91 # define GENX(X) X##_v7 macro
H A Ddecode.h87 void GENX(pandecode_jc)(mali_ptr jc_gpu_va, unsigned gpu_id);
88 void GENX(pandecode_abort_on_fault)(mali_ptr jc_gpu_va);
/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/
H A Dpan_indirect_dispatch.h40 GENX(pan_indirect_dispatch_emit)(struct pan_pool *pool,
45 GENX(pan_indirect_dispatch_init)(struct panfrost_device *dev);
48 GENX(pan_indirect_dispatch_cleanup)(struct panfrost_device *dev);
H A Dpan_indirect_draw.h52 GENX(panfrost_emit_indirect_draw)(struct pan_pool *pool,
58 GENX(panfrost_init_indirect_draw_shaders)(struct panfrost_device *dev,
62 GENX(panfrost_cleanup_indirect_draw_shaders)(struct panfrost_device *dev);
H A Dpan_cs.h148 GENX(pan_emit_tls)(const struct pan_tls_info *info,
152 GENX(pan_select_crc_rt)(const struct pan_fb_info *fb);
159 GENX(pan_select_crc_rt)(fb) >= 0);
163 GENX(pan_emit_fbd)(const struct panfrost_device *dev,
171 GENX(pan_emit_tiler_heap)(const struct panfrost_device *dev,
175 GENX(pan_emit_tiler_ctx)(const struct panfrost_device *dev,
183 GENX(pan_emit_fragment_job)(const struct pan_fb_info *fb,
H A Dpan_blitter.h85 GENX(pan_blitter_init)(struct panfrost_device *dev,
90 GENX(pan_blitter_cleanup)(struct panfrost_device *dev);
93 GENX(pan_preload_fb)(struct pan_pool *desc_pool,
100 GENX(pan_blit_ctx_init)(struct panfrost_device *dev,
124 GENX(pan_blit)(struct pan_blit_context *ctx,
H A Dpan_blend.h161 GENX(pan_blend_create_shader)(const struct panfrost_device *dev,
169 GENX(pan_blend_get_internal_desc)(const struct panfrost_device *dev,
178 GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
/xsrc/external/mit/MesaLib/dist/src/intel/genxml/
H A Dgen_macros.h29 * The prefixing macros GENX() and genX() automatically prefix whatever you
63 # define GENX(X) GFX4_##X macro
66 # define GENX(X) GFX45_##X macro
69 # define GENX(X) GFX5_##X macro
72 # define GENX(X) GFX6_##X macro
75 # define GENX(X) GFX7_##X macro
78 # define GENX(X) GFX75_##X macro
81 # define GENX(X) GFX8_##X macro
84 # define GENX(X) GFX9_##X macro
87 # define GENX( macro
90 # define GENX macro
93 # define GENX macro
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/genxml/
H A Dgen_macros.h29 * The prefixing macros GENX() and genX() automatically prefix whatever you
65 # define GENX(X) GEN4_##X macro
68 # define GENX(X) GEN45_##X macro
71 # define GENX(X) GEN5_##X macro
74 # define GENX(X) GEN6_##X macro
77 # define GENX(X) GEN7_##X macro
80 # define GENX(X) GEN75_##X macro
83 # define GENX(X) GEN8_##X macro
86 # define GENX(X) GEN9_##X macro
89 # define GENX( macro
92 # define GENX macro
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_state.c49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
82 anv_pack_struct(&cache_mode_0, GENX(CACHE_MODE_0));
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
85 lri.RegisterOffset = GENX(CACHE_MODE_0_num);
94 device->default_mocs = GENX(MOCS);
96 device->external_mocs = GENX(EXTERNAL_MOCS);
107 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
116 anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
122 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IM
[all...]
H A DgenX_gpu_memcpy.c86 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
87 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
88 &(struct GENX(VERTEX_BUFFER_STATE)) {
101 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
102 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
103 &(struct GENX(VERTEX_ELEMENT_STATE)) {
115 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
119 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
120 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
121 anv_batch_emit(&cmd_buffer->batch, GENX(
[all...]
H A Dgen8_cmd_buffer.c50 struct GENX(SF_CLIP_VIEWPORT) sf_clip_viewport = {
67 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64,
72 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
90 struct GENX(CC_VIEWPORT) cc_viewport = {
95 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
99 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
122 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
131 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
134 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
135 lri.RegisterOffset = GENX(CACHE_MODE_0_nu
[all...]
H A DgenX_pipeline.c115 GENX(3DSTATE_VERTEX_ELEMENTS));
137 struct GENX(VERTEX_ELEMENT_STATE) element = {
144 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
165 struct GENX(VERTEX_ELEMENT_STATE) element = {
176 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
183 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
207 struct GENX(VERTEX_ELEMENT_STATE) element = {
221 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
225 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) {
237 struct GENX(VERTEX_ELEMENT_STAT
[all...]
H A Dgen7_cmd_buffer.c187 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
188 struct GENX(3DSTATE_SF) sf = {
189 GENX(3DSTATE_SF_header),
196 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
205 GENX(COLOR_CALC_STATE_length) * 4,
207 struct GENX(COLOR_CALC_STATE) cc = {
215 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
217 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
226 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
228 struct GENX(DEPTH_STENCIL_STAT
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_gpu_memcpy.c87 dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));
88 GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,
89 &(struct GENX(VERTEX_BUFFER_STATE)) {
105 dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));
106 GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,
107 &(struct GENX(VERTEX_ELEMENT_STATE)) {
119 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
126 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);
130 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);
131 anv_batch_emit(&cmd_buffer->batch, GENX(
[all...]
H A Dgfx8_cmd_buffer.c52 struct GENX(SF_CLIP_VIEWPORT) sfv = {
85 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_state.map + i * 64, &sfv);
89 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), clip) {
115 struct GENX(CC_VIEWPORT) cc_viewport = {
120 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map + i * 8, &cc_viewport);
124 GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
164 anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0),
167 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
168 lri.RegisterOffset = GENX(CACHE_MODE_0_nu
[all...]
H A DgenX_state.c89 unsigned size = GENX(SLICE_HASH_TABLE_length) * 4;
95 struct GENX(SLICE_HASH_TABLE) table;
98 GENX(SLICE_HASH_TABLE_pack)(NULL, device->slice_hash.map, &table);
101 anv_batch_emit(batch, GENX(3DSTATE_SLICE_TABLE_STATE_POINTERS), ptr) {
106 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), mode) {
130 anv_batch_emit(batch, GENX(3DSTATE_SUBSLICE_HASH_TABLE), p) {
148 anv_batch_emit(batch, GENX(3DSTATE_3D_MODE), p) {
166 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) {
175 anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) {
185 anv_batch_emit(&batch, GENX(
[all...]
H A Dgfx7_cmd_buffer.c245 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
246 struct GENX(3DSTATE_SF) sf = {
247 GENX(3DSTATE_SF_header),
260 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
269 GENX(COLOR_CALC_STATE_length) * 4,
271 struct GENX(COLOR_CALC_STATE) cc = {
279 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
281 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
287 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
304 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_lengt
[all...]
H A DgenX_query.c219 anv_batch_emit(&batch, GENX(MI_BATCH_BUFFER_END), bbe);
611 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
638 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
800 GENX(IA_VERTICES_COUNT_num),
801 GENX(IA_PRIMITIVES_COUNT_num),
802 GENX(VS_INVOCATION_COUNT_num),
803 GENX(GS_INVOCATION_COUNT_num),
804 GENX(GS_PRIMITIVES_COUNT_num),
805 GENX(CL_INVOCATION_COUNT_num),
806 GENX(CL_PRIMITIVES_COUNT_nu
[all...]
H A DgenX_pipeline.c117 GENX(3DSTATE_VERTEX_ELEMENTS));
139 struct GENX(VERTEX_ELEMENT_STATE) element = {
146 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + i * 2], &element);
167 struct GENX(VERTEX_ELEMENT_STATE) element = {
178 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
185 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
209 struct GENX(VERTEX_ELEMENT_STATE) element = {
223 GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element);
226 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
233 anv_batch_emit(&pipeline->base.batch, GENX(
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/isl/
H A Disl_emit_depth_stencil.c65 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
66 GENX(3DSTATE_DEPTH_BUFFER_header),
125 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
126 GENX(3DSTATE_STENCIL_BUFFER_header),
151 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
152 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
154 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
155 GENX(3DSTATE_CLEAR_PARAMS_header),
210 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
211 dw += GENX(
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_emit_depth_stencil.c72 struct GENX(3DSTATE_DEPTH_BUFFER) db = {
73 GENX(3DSTATE_DEPTH_BUFFER_header),
161 struct GENX(3DSTATE_STENCIL_BUFFER) sb = {
162 GENX(3DSTATE_STENCIL_BUFFER_header),
220 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = {
221 GENX(3DSTATE_HIER_DEPTH_BUFFER_header),
223 struct GENX(3DSTATE_CLEAR_PARAMS) clear = {
224 GENX(3DSTATE_CLEAR_PARAMS_header),
322 GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db);
323 dw += GENX(
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_genX_exec.h309 struct GENX(VERTEX_BUFFER_STATE) *vb,
342 struct GENX(VERTEX_BUFFER_STATE) vb[3]; local in function:blorp_emit_vertex_buffers
357 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
358 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
363 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]);
364 dw += GENX(VERTEX_BUFFER_STATE_length);
377 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; local in function:blorp_emit_vertex_elements
428 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
460 ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
474 ve[slot] = (struct GENX(VERTEX_ELEMENT_STAT
1018 struct GENX(BLEND_STATE) blend; local in function:blorp_emit_blend_state
1031 struct GENX(BLEND_STATE_ENTRY) entry = { local in function:blorp_emit_blend_state
1093 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = { local in function:blorp_emit_depth_stencil_state
1431 struct GENX(RENDER_SURFACE_STATE) ss = { local in function:blorp_emit_null_surface_state
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h246 blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
254 blorp_emit(batch, GENX(3DSTATE_URB_VS), urb) {
362 blorp_fill_vertex_buffer_state(struct GENX(VERTEX_BUFFER_STATE) *vb,
399 struct GENX(VERTEX_BUFFER_STATE) vb[3]; local in function:blorp_emit_vertex_buffers
414 const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
415 uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
420 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]);
421 dw += GENX(VERTEX_BUFFER_STATE_length);
434 struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements]; local in function:blorp_emit_vertex_elements
485 ve[slot] = (struct GENX(VERTEX_ELEMENT_STAT
1097 struct GENX(BLEND_STATE) blend = { }; local in function:blorp_emit_blend_state
1109 struct GENX(BLEND_STATE_ENTRY) entry = { local in function:blorp_emit_blend_state
1171 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = { local in function:blorp_emit_depth_stencil_state
1526 struct GENX(RENDER_SURFACE_STATE) ss = { local in function:blorp_emit_null_surface_state
2197 struct GENX(INTERFACE_DESCRIPTOR_DATA) idd = { local in function:blorp_exec_compute
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_state.c476 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
481 #define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
486 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
530 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
555 iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
578 iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) {
595 _iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) {
616 iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) {
640 iris_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
668 iris_emit_cmd(batch, GENX(PIPELINE_SELEC
[all...]

Completed in 20 milliseconds

123