Searched refs:GFX6 (Results 1 - 25 of 71) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_gfx_ver_enum.h31 GFX6 = (1 << 3), enumerator in enum:gfx_ver
54 case 60: return GFX6;
H A Dbrw_eu.cpp647 { BRW_OPCODE_CASE, 38, "case", 0, 0, GFX6 },
654 { BRW_OPCODE_CALL, 44, "call", 0, 0, GFX_GE(GFX6) },
656 { BRW_OPCODE_RET, 45, "ret", 0, 0, GFX_GE(GFX6) },
658 { BRW_OPCODE_FORK, 46, "fork", 0, 0, GFX6 },
668 { BRW_OPCODE_MATH, 56, "math", 2, 1, GFX_GE(GFX6) },
695 { BRW_OPCODE_MAD, 91, "mad", 3, 1, GFX_GE(GFX6) },
696 { BRW_OPCODE_LRP, 92, "lrp", 3, 1, GFX_GE(GFX6) & GFX_LE(GFX10) },
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dtest_tests.cpp56 for (int cls = GFX6; cls <= GFX7; cls++) {
H A Dframework.h50 snprintf(buf, sizeof(buf), "gfx%d%s", cls - GFX6 + 6, rest);
H A Dtest_assembler.cpp29 for (unsigned i = GFX6; i <= GFX10; i++) {
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Damd_family.h82 CHIP_TAHITI, /* GFX6 (Southern Islands) */
130 GFX6, enumerator in enum:chip_class
H A Dac_rgp.c66 SQTT_VERSION_2_0 = 0x3, /* GFX6 */
371 case GFX6:
735 case GFX6:
811 case GFX6:
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.0.5.rst188 - ac/nir: split 8-bit load/store to global memory on GFX6
189 - ac/nir: split 8-bit SSBO stores on GFX6
190 - radv/llvm: enable 8-bit storage features on GFX6-GFX7
191 - ac/nir: split 16-bit load/store to global memory on GFX6
192 - ac/nir: split 16-bit SSBO stores on GFX6
193 - radv/llvm: enable 16-bit storage features on GFX6-GFX7
H A D20.0.0.rst44 - GFX6 (Southern Islands) and GFX7 (Sea Islands) support on RADV/ACO.
64 - aco: wrong geometry with Assassins Creed Origins on GFX6
78 - aco: implement GFX6 support
85 - aco: Dead Rising 4 crashes in lower_to_hw_instr() on GFX6-GFX7
125 fail on GFX6-GFX8
3044 - radv: hardcode the number of waves for the GFX6 LS-HS bug
3069 - radv: enable VK_KHR_shader_subgroup_extended_types on GFX6-GFX7
3124 - radv: handle unaligned vertex fetches on GFX6/GFX10
3177 - aco: fix emitting SMEM instructions with no operands on GFX6-GFX7
3179 GFX6
[all...]
H A D19.3.2.rst46 fail on GFX6-GFX8
H A D20.0.7.rst157 - aco: fix 64-bit trunc with negative exponents on GFX6
H A D20.1.9.rst49 - ac/surface: Fix depth import on GFX6-GFX8.
H A D20.3.3.rst129 - radv/llvm,aco: always split typed vertex buffer loads on GFX6 and GFX10+
H A D21.0.2.rst135 - aco/isel: Don't emit unsupported i16<->f16 conversion opcodes on GFX6/7
H A D21.1.3.rst134 - aco: fix range checking for SSBO loads/stores with SGPR offset on GFX6-7
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_llvm_util.h141 /* GFX6 only supports vec3 with load/store format. */
142 return chip != GFX6 || use_format;
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c97 info->chip_class = GFX6;
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c275 ws->info.chip_class = GFX6;
566 if (ws->info.chip_class >= GFX6) {
577 ws->info.gfx_ib_pad_with_type2 = ws->info.chip_class <= GFX6 ||
595 (ws->info.chip_class == GFX6 &&
597 /* GFX6 doesn't support unaligned loads. */
602 ws->info.has_2d_tiling = ws->info.chip_class <= GFX6 || ws->info.drm_minor >= 35;
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME-ISA.md84 does not seem to be the case on GFX8 and GFX9 (GFX6 and GFX7 are untested). It
191 ## GCN / GFX6 hazards
196 followed by a read with `v_readfirstlane` or `v_readlane` to fix GPU hangs on GFX6.
H A DREADME.md169 ##### GFX6-8:
176 | GFX6-8 HW stages: | LS | HS | ES | GS | VS | PS | ACO terminology |
210 GFX6-10:
214 | GFX6-10 HW stage | CS | ACO terminology |
H A Daco_print_asm.cpp52 case GFX6:
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_cp_dma.c63 assert(sctx->chip_class != GFX6 || cache_policy == L2_BYPASS);
487 if (sctx->chip_class == GFX6 && dst_sel == V_370_MEM)
H A Dsi_test_dma_perf.c111 if (sctx->chip_class == GFX6) {
112 /* GFX6 doesn't support CP DMA operations through L2. */
115 /* WAVES_PER_SH is in multiples of 16 on GFX6. */
H A Dsi_state_draw.cpp34 #define GFX(name) name##GFX6
275 if (GFX_VERSION == GFX6)
412 /* GFX6 doesn't support the L2 prefetch. */
453 /* GFX6-GFX8 */
519 bool has_primid_instancing_bug = sctx->chip_class == GFX6 && sctx->screen->info.max_se == 1;
640 if (sctx->chip_class == GFX6) {
641 /* GFX6 bug workaround, related to power management. Limit LS-HS
655 * doesn't work correctly on GFX6 when there is no other
1709 case GFX6:
1710 si_set_vb_descriptor<GFX6>(velem
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_shader.h620 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
621 if (chip_class == GFX6) {

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