Searched refs:GFX8 (Results 1 - 25 of 95) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_gfx_ver_enum.h34 GFX8 = (1 << 6), enumerator in enum:gfx_ver
57 case 80: return GFX8;
H A Dbrw_eu.cpp615 { BRW_OPCODE_SMOV, 10, "smov", 0, 0, GFX_GE(GFX8) & GFX_LT(GFX12) },
627 { BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
659 { BRW_OPCODE_GOTO, 46, "goto", 0, 0, GFX_GE(GFX8) },
697 { BRW_OPCODE_MADM, 93, "madm", 3, 1, GFX_GE(GFX8) },
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/
H A Dtest_isel.cpp62 for (unsigned i = GFX7; i <= GFX8; i++) {
85 for (unsigned i = GFX8; i <= GFX10; i++) {
114 for (unsigned i = GFX8; i <= GFX10; i++) {
H A Dtest_builder.cpp29 for (unsigned i = GFX8; i <= GFX10; i++) {
H A Dtest_sdwa.cpp30 for (unsigned i = GFX8; i <= GFX10; i++) {
57 //~gfx7! SDWA is GFX8+ only: v1: %t0 = v_mul_f32 %a, %b dst_sel:dword src0_sel:dword src1_sel:dword
67 for (unsigned i = GFX8; i <= GFX10; i++) {
96 for (unsigned i = GFX8; i <= GFX10; i++) {
104 //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword
107 //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword
117 for (unsigned i = GFX8; i <= GFX10; i++) {
133 for (unsigned i = GFX8; i <= GFX10; i++) {
278 for (unsigned i = GFX8; i <= GFX10; i++) {
335 for (unsigned i = GFX8;
[all...]
H A Dtest_regalloc.cpp38 for (chip_class cc = GFX8; cc < NUM_GFX_VERSIONS; cc = (chip_class)((unsigned)cc + 1)) {
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Damd_family.h91 CHIP_TONGA, /* GFX8 (Volcanic Islands & Polaris) */
132 GFX8, enumerator in enum:chip_class
H A Dac_shader_util.c104 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= GFX8) | S_028A40_GS_WRITE_OPTIMIZE(1) |
256 if (dim == ac_image_cube || (chip_class <= GFX8 && dim == ac_image_3d))
557 if (chip_class <= GFX8)
H A Dac_gpu_info.c642 info->chip_class = GFX8;
711 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
712 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2;
852 info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2);
868 info->chip_class >= GFX8 && info->chip_class <= GFX9 && info->max_se >= 2;
882 info->chip_class >= GFX9 || (info->chip_class >= GFX8 && info->me_fw_feature >= 41);
884 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
888 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 && info->chip_class <= GFX9;
1072 } else if (info->chip_class >= GFX8) {
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c93 info->chip_class = GFX8;
120 else if (info->chip_class >= GFX8)
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_print_asm.cpp68 case GFX8:
295 if (program->chip_class >= GFX8) {
296 /* LLVM disassembler only supports GFX8+ */
315 if (program->chip_class >= GFX8) {
H A Daco_ir.cpp80 case GFX8: program->family = CHIP_POLARIS10; break;
112 } else if (program->chip_class >= GFX8) {
135 /* GFX8 APUs */
190 if (chip < GFX8 || instr->isDPP() || instr->isVOP3P())
200 if (vop3.clamp && instr->isVOPC() && chip != GFX8)
234 if (chip != GFX8 && is_mac)
238 if (!pre_ra && instr->isVOPC() && chip == GFX8)
284 if (instr->definitions[0].getTemp().type() == RegType::sgpr && chip == GFX8)
H A Daco_assembler.cpp245 GFX8 and below) */
263 assert(ctx.chip_class >= GFX9); /* GFX8 and below don't support specifying a constant
310 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
333 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
355 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
391 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
427 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
561 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
592 if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9)
670 assert(ctx.chip_class >= GFX8);
[all...]
H A Daco_lower_to_hw_instr.cpp82 } else if (chip >= GFX8) {
92 } else if (chip >= GFX8) {
104 } else if (chip >= GFX8) {
114 } else if (chip >= GFX8) {
124 } else if (chip >= GFX8) {
134 } else if (chip >= GFX8) {
514 if (ctx->program->chip_class >= GFX8) {
671 } else if (ctx->program->chip_class >= GFX8) {
1048 if (op.bytes() == 4 && op.constantEquals(0x3e22f983) && ctx->program->chip_class >= GFX8)
1049 op.setFixed(PhysReg{248}); /* it can be an inline constant on GFX8
[all...]
H A Daco_validate.cpp155 check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
161 check(sdwa.clamp == false || program->chip_class == GFX8,
162 "SDWA VOPC clamp only supported on GFX8", instr.get());
165 "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
217 program->chip_class == GFX8 &&
728 if (instr->isPseudo() && chip >= GFX8)
783 if (instr->isPseudo() && chip >= GFX8)
815 return chip >= GFX8 ? def.bytes() : def.size() * 4u;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_draw.cpp38 #define GFX(name) name##GFX8
149 if (!HAS_GS || GFX_VERSION <= GFX8) {
156 assert(GFX_VERSION <= GFX8);
165 if (GFX_VERSION <= GFX8) {
192 if (GFX_VERSION <= GFX8) {
200 if ((!HAS_TESS && !HAS_GS) || GFX_VERSION <= GFX8) {
307 if ((GFX_VERSION <= GFX8 &&
314 if (GFX_VERSION <= GFX8) /* LS */
320 if (GFX_VERSION <= GFX8) /* ES */
328 if (GFX_VERSION <= GFX8) /* E
[all...]
H A Dsi_gpu_load.c104 if (sscreen->info.chip_class == GFX7 || sscreen->info.chip_class == GFX8) {
112 if (sscreen->info.chip_class >= GFX8) {
H A Dsi_state.c106 if (sctx->chip_class >= GFX8) {
592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10)
603 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable)
1725 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1727 if (sscreen->info.chip_class <= GFX8)
2483 } else if (sctx->chip_class >= GFX8) {
2585 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2599 /* GFX6-GFX8 */
3203 /* Compute mutable surface parameters (GFX6-GFX8). */
3245 sctx->chip_class >= GFX8
[all...]
H A Dsi_texture.c194 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
197 if (sscreen->info.chip_class == GFX8)
208 if (sscreen->info.chip_class >= GFX8) {
230 case GFX8:
548 if (sscreen->info.chip_class <= GFX8)
699 /* Since shader image stores don't support DCC on GFX8,
924 /* On GFX8, HTILE uses different tiling depending on the TC_COMPATIBLE_HTILE
930 tex->tc_compatible_htile = (sscreen->info.chip_class == GFX8 &&
933 (sscreen->info.chip_class >= GFX8 &&
938 * - GFX8 onl
[all...]
H A Dsi_pipe.c140 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8;
484 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
620 case GFX8:
1251 if (sscreen->info.chip_class >= GFX8)
1262 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1339 if (sscreen->info.chip_class <= GFX8) {
H A Dsi_fence.c114 if (ctx->chip_class == GFX7 || ctx->chip_class == GFX8) {
152 if (screen->info.chip_class == GFX7 || screen->info.chip_class == GFX8)
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dsi_cmd_buffer.c140 assert(device->physical_device->rad_info.chip_class == GFX8);
198 if (physical_device->rad_info.chip_class <= GFX8)
206 if (physical_device->rad_info.chip_class <= GFX8) {
449 } else if (physical_device->rad_info.chip_class >= GFX8) {
532 assert(device->physical_device->rad_info.chip_class == GFX8);
772 if (chip_class <= GFX8 && info->max_se == 4 && multi_instances_smaller_than_primgroup)
779 /* Required by Hawaii and, for some special cases, by GFX8. */
782 (chip_class == GFX8 &&
801 if (chip_class <= GFX8 && ia_switch_on_eoi)
901 if (chip_class == GFX7 || chip_class == GFX8) {
[all...]
H A Dradv_sqtt.c218 assert(device->physical_device->rad_info.chip_class == GFX8);
351 /* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
364 } else if (device->physical_device->rad_info.chip_class >= GFX8) {
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.3.5.rst163 - ac/llvm: fix 16-bit fmed3 on GFX8 and older gens
164 - ac/llvm: flush denorms for nir_op_fmed3 on GFX8 and older gens
H A D20.0.1.rst165 - ac/llvm: fix 16-bit fmed3 on GFX8 and older gens
166 - ac/llvm: flush denorms for nir_op_fmed3 on GFX8 and older gens

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