Searched refs:GP_BLIT_STATUS (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Drndr_gu1.c49 while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { ; }
51 while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { ; }
53 while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { ; }
56 while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { INB (0x80); }
58 while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { INB (0x80); }
60 while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { INB (0x80); }
112 WRITE_REG32(GP_BLIT_STATUS, control);
1508 if (READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING)
H A Ddisp_gu1.c510 /* ALSO WRITE GP_BLIT_STATUS FOR PITCH AND 8/18 BPP */
520 WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value);
755 value = (unsigned long) READ_REG16(GP_BLIT_STATUS);
764 WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value);
H A Dgfx_regs.h63 #define GP_BLIT_STATUS 0x820C /* blit status register */ macro
86 /* "GP_BLIT_STATUS" BIT DEFINITIONS */
/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Drndr_gu1.c201 #define GFX_WAIT_PENDING while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { ; }
202 #define GFX_WAIT_BUSY while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { ; }
203 #define GFX_WAIT_PIPELINE while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { ; }
205 #define GFX_WAIT_PENDING while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { INB (0x80); }
206 #define GFX_WAIT_BUSY while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { INB (0x80); }
207 #define GFX_WAIT_PIPELINE while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { INB (0x80); }
262 WRITE_REG32(GP_BLIT_STATUS, control);
1651 if (READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING)
H A Ddisp_gu1.c767 /* ALSO WRITE GP_BLIT_STATUS FOR PITCH AND 8/18 BPP */
777 WRITE_REG16(GP_BLIT_STATUS, (unsigned short)value);
1026 value = (unsigned long)READ_REG16(GP_BLIT_STATUS);
1035 WRITE_REG16(GP_BLIT_STATUS, (unsigned short)value);
H A Dgfx_regs.h164 #define GP_BLIT_STATUS 0x820C /* blit status register */ macro
187 /* "GP_BLIT_STATUS" BIT DEFINITIONS */
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_gx1_accel.c202 #define GFX_WAIT_BUSY while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { ; }
203 #define GFX_WAIT_PENDING while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { ; }

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