Searched refs:HS (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_program.c132 HS = 2, enumerator in enum:__anon4fcc07340103
146 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
193 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
194 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
287 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
288 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
289 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
290 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
410 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
411 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS]
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c252 HS = 2, enumerator in enum:__anon68029e760103
266 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
316 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
373 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
374 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
375 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
391 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
392 COND(s[HS].v && s[HS].v->has_ssbo, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
405 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS]
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c164 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES }; enumerator in enum:__anonb59db1490103
174 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
225 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
305 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
306 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
307 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
325 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
326 COND(s[HS].v && s[HS].v->has_ssbo,
342 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS]
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_program.c91 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES }; enumerator in enum:__anon9d671a070103
101 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
149 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
150 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
256 A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
257 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
258 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
259 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
392 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
393 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS]
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/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME.md126 * TCS = Tessellation Control Shader, equivalent to D3D HS = Hull Shader
134 * LS = Local Shader (merged into HS on GFX9+), only runs SW VS when tessellation is used
135 * HS = Hull Shader, the HW equivalent of a Tessellation Control Shader, runs before the fixed function hardware performs tessellation
172 * LS and HS share the same LDS space, so LS can store its output to LDS, where HS can read it
173 * HS, ES, GS outputs are stored in VRAM, next stage reads these from VRAM
176 | GFX6-8 HW stages: | LS | HS | ES | GS | VS | PS | ACO terminology |
185 * HW LS and HS stages are merged, and the merged shader still uses LDS in the same way as before
H A Daco_instruction_selection_setup.cpp862 hw_stage = HWStage::HS; /* GFX6-8: TCS is a Hull Shader */
864 hw_stage = HWStage::HS; /* GFX9-10: VS+TCS merged into a Hull Shader */
H A Daco_ir.h1941 LS, /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */
1942 HS, /* Hull shader: TCS on GFX6-8. Merged VS and TCS on GFX9-10. */ enumerator in enum:aco::HWStage
1988 static constexpr Stage vertex_tess_control_hs(HWStage::HS, SWStage::VS_TCS);
1993 static constexpr Stage tess_control_hs(HWStage::HS, SWStage::TCS);
H A Daco_instruction_selection.cpp7074 ctx->stage.hw == HWStage::HS ||
7082 ctx->stage.hw == HWStage::CS || ctx->stage.hw == HWStage::HS || ctx->stage.hw == HWStage::NGG;
8188 if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
11287 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
11577 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_program.c250 HS = 2, enumerator in enum:__anon803935b80103
271 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
375 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
376 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
413 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.1.9.rst52 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
H A D17.2.2.rst104 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
H A D11.0.3.rst119 - radeonsi: don't forget to update scratch relocations for LS, HS, ES
H A D19.3.0.rst2170 - freedreno: Add state binding functions for HS/DS/GS
2172 - freedreno/a6xx: Add generic program stateobj support for HS/DS/GS
2173 - freedreno/ir3: Add HS/DS/GS to shader key and cache
2174 - freedreno/a6xx: Emit const and texture state for HS/DS/GS
2176 - freedreno/registers: Update with GS, HS and DS registers
H A D21.0.0.rst2084 - radeonsi: adjust tess SGPRs to allow fully occupied 3 HS waves of triangles
2085 - radeonsi: don't leave more than 8 unoccupied lanes in HS
2087 - radeonsi: limit HS LDS usage per workgroup to 16K to allow at least 2 WGs/CU
H A D20.1.0.rst4188 - aco: Don't generate an if when the first part of a merged HS or GS is
4214 - aco: When LS and HS invocations are the same, pass LS outputs in
H A D20.2.0.rst1017 - turnip: Emit HS/DS user consts as draw states
3336 - radeonsi: always use Wave64 for HS/GS/VS shader stages (except GS fast launch)
H A D20.0.0.rst3044 - radv: hardcode the number of waves for the GFX6 LS-HS bug
H A D21.3.0.rst932 - ir3: Add bar to beginning of HS with tess_use_shared
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json9697 "description": "microsoft/compiler: Handle load_output in the HS stage as reading a previously written patch constant",
9724 "description": "microsoft/compiler: For store_output from HS, use storePatchConstant",
9787 "description": "microsoft/compiler: Emit HS PSV validation and entrypoint metadata",
9814 "description": "microsoft/compiler: Handle store_per_vertex_output for HS outputs",
11254 "description": "microsoft/compiler: Handle load_invocation_id for GS and HS",
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