Searched refs:I915_CTXREG_LIS5 (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_state.c115 set_ctx_bits(I915_CTXREG_LIS5,
211 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
228 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
230 i915->state.Ctx[I915_CTXREG_LIS5] = dw0;
695 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
709 if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
711 i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
813 dw = i915->state.Ctx[I915_CTXREG_LIS5];
818 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
819 i915->state.Ctx[I915_CTXREG_LIS5]
[all...]
H A Di915_context.h84 #define I915_CTXREG_LIS5 5 macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_state.c115 set_ctx_bits(I915_CTXREG_LIS5,
211 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
228 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
230 i915->state.Ctx[I915_CTXREG_LIS5] = dw0;
695 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK;
709 if (tmp != i915->state.Ctx[I915_CTXREG_LIS5]) {
711 i915->state.Ctx[I915_CTXREG_LIS5] = tmp;
813 dw = i915->state.Ctx[I915_CTXREG_LIS5];
818 if (dw != i915->state.Ctx[I915_CTXREG_LIS5]) {
819 i915->state.Ctx[I915_CTXREG_LIS5]
[all...]
H A Di915_context.h84 #define I915_CTXREG_LIS5 5 macro

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