| /xsrc/external/mit/MesaLib.old/dist/src/intel/tools/ |
| H A D | aubinator_error_decode.c | 86 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_ACTHD_UDW" },
87 { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_ACTHD_UDW" },
94 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_RING_BUFFER_CTL" },
95 { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_RING_BUFFER_CTL" },
102 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_FAULT_REG" },
113 [I915_ENGINE_CLASS_VIDEO] = "vcs",
131 { "bsd", I915_ENGINE_CLASS_VIDEO, 0 },
132 { "bsd2", I915_ENGINE_CLASS_VIDEO, 1 },
187 case I915_ENGINE_CLASS_VIDEO:
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| H A D | aub_read.c | 158 engine = I915_ENGINE_CLASS_VIDEO;
206 engine = I915_ENGINE_CLASS_VIDEO;
244 engine = I915_ENGINE_CLASS_VIDEO;
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| H A D | aub_write.c | 376 [I915_ENGINE_CLASS_VIDEO] = {
378 .engine_class = I915_ENGINE_CLASS_VIDEO,
402 case I915_ENGINE_CLASS_VIDEO:
419 [I915_ENGINE_CLASS_VIDEO] = gen8_video_context_init,
424 [I915_ENGINE_CLASS_VIDEO] = gen10_video_context_init,
503 write_engine_execlist_setup(aub, I915_ENGINE_CLASS_VIDEO);
506 register_write_out(aub, HWS_PGA_VCSUNIT0, aub->engine_setup[I915_ENGINE_CLASS_VIDEO].pphwsp_addr);
722 [I915_ENGINE_CLASS_VIDEO] = AUB_TRACE_TYPE_RING_PRB1,
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| H A D | error2aub.c | 214 { "vcs", I915_ENGINE_CLASS_VIDEO, true },
220 { "bsd command stream", I915_ENGINE_CLASS_VIDEO, false },
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| H A D | intel_dump_gpu.c | 198 return I915_ENGINE_CLASS_VIDEO;
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| /xsrc/external/mit/MesaLib/dist/src/intel/tools/ |
| H A D | aub_read.c | 156 engine = I915_ENGINE_CLASS_VIDEO;
204 engine = I915_ENGINE_CLASS_VIDEO;
242 engine = I915_ENGINE_CLASS_VIDEO;
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| H A D | aub_write.h | 77 struct aub_hw_context hw_contexts[I915_ENGINE_CLASS_VIDEO + 1];
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| H A D | aubinator_error_decode.c | 82 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_ACTHD_UDW" },
83 { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_ACTHD_UDW" },
90 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_RING_BUFFER_CTL" },
91 { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_RING_BUFFER_CTL" },
98 { I915_ENGINE_CLASS_VIDEO, 0, "VCS_FAULT_REG" },
109 [I915_ENGINE_CLASS_VIDEO] = "vcs",
127 { "bsd", I915_ENGINE_CLASS_VIDEO, 0 },
128 { "bsd2", I915_ENGINE_CLASS_VIDEO, 1 },
183 case I915_ENGINE_CLASS_VIDEO:
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| H A D | aub_write.c | 367 [I915_ENGINE_CLASS_VIDEO] = {
369 .engine_class = I915_ENGINE_CLASS_VIDEO,
456 case I915_ENGINE_CLASS_VIDEO:
473 [I915_ENGINE_CLASS_VIDEO] = gfx8_video_context_init,
478 [I915_ENGINE_CLASS_VIDEO] = gfx10_video_context_init,
509 case I915_ENGINE_CLASS_VIDEO: reg = HWS_PGA_VCSUNIT0; break;
783 [I915_ENGINE_CLASS_VIDEO] = AUB_TRACE_TYPE_RING_PRB1,
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| H A D | error2aub.c | 201 { "vcs", I915_ENGINE_CLASS_VIDEO, true },
207 { "bsd command stream", I915_ENGINE_CLASS_VIDEO, false },
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| H A D | intel_dump_gpu.c | 197 return I915_ENGINE_CLASS_VIDEO;
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/common/ |
| H A D | gen_decoder.c | 169 I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO) |
190 group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO);
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| /xsrc/external/mit/MesaLib/dist/src/intel/common/ |
| H A D | intel_decoder.c | 169 I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO) |
190 group->engine_mask |= I915_ENGINE_CLASS_TO_MASK(I915_ENGINE_CLASS_VIDEO);
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| /xsrc/external/mit/libdrm/dist/include/drm/ |
| H A D | i915_drm.h | 190 * @I915_ENGINE_CLASS_VIDEO:
196 I915_ENGINE_CLASS_VIDEO = 2, enumerator in enum:drm_i915_gem_engine_class
2170 * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
2171 * { I915_ENGINE_CLASS_VIDEO, 1 }, },
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| /xsrc/external/mit/MesaLib.old/dist/include/drm-uapi/ |
| H A D | i915_drm.h | 99 I915_ENGINE_CLASS_VIDEO = 2, enumerator in enum:drm_i915_gem_engine_class
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| /xsrc/external/mit/MesaLib/dist/include/drm-uapi/ |
| H A D | i915_drm.h | 167 I915_ENGINE_CLASS_VIDEO = 2, enumerator in enum:drm_i915_gem_engine_class
1939 * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
1940 * { I915_ENGINE_CLASS_VIDEO, 1 }, },
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