Searched refs:I915_MAX_TEX_INSN (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_context.h126 #define I915_MAX_TEX_INSN 32 macro
132 I915_MAX_TEX_INSN + \
170 GLuint program[(I915_MAX_TEX_INSN + I915_MAX_ALU_INSN) * 3];
H A Di915_context.c234 ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeTexInstructions = I915_MAX_TEX_INSN;
236 I915_MAX_TEX_INSN);
H A Di915_program.c505 if (p->nr_tex_insn > I915_MAX_TEX_INSN) {
507 p->nr_tex_insn, I915_MAX_TEX_INSN);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_context.h126 #define I915_MAX_TEX_INSN 32 macro
132 I915_MAX_TEX_INSN + \
170 GLuint program[(I915_MAX_TEX_INSN + I915_MAX_ALU_INSN) * 3];
H A Di915_context.c235 ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxNativeTexInstructions = I915_MAX_TEX_INSN;
237 I915_MAX_TEX_INSN);
H A Di915_program.c505 if (p->nr_tex_insn > I915_MAX_TEX_INSN) {
507 p->nr_tex_insn, I915_MAX_TEX_INSN);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_screen.c131 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
135 return I915_MAX_TEX_INSN;
H A Di915_reg.h486 #define I915_MAX_TEX_INSN 32 macro
H A Di915_fpc_translate.c1121 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_screen.c322 return I915_MAX_ALU_INSN + I915_MAX_TEX_INSN;
326 return I915_MAX_TEX_INSN;
H A Di915_reg.h457 #define I915_MAX_TEX_INSN 32 macro
H A Di915_fpc_translate.c917 if (p->nr_tex_insn > I915_MAX_TEX_INSN)
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_reg.h475 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_reg.h475 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_reg.h475 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_reg.h475 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_reg.h495 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h478 #define I915_MAX_TEX_INSN 32 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h478 #define I915_MAX_TEX_INSN 32 macro

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