Searched refs:INREG (Results 1 - 25 of 93) sorted by relevance

1234

/xsrc/external/mit/xf86-video-neomagic/dist/src/
H A Dneo_macros.h39 while( INREG(NEOREG_BLTSTAT) & NEO_BS0_FIFO_PEND); \
43 while( INREG(NEOREG_BLTSTAT) & NEO_BS0_BLT_BUSY); \
53 NeoFifoCount = (INREG(NEOREG_BLTSTAT) >> 8); \
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_vip.c58 timeout = INREG(RADEON_VIPH_TIMEOUT_STAT);
64 return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
67 return (INREG(RADEON_VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
79 timeout = INREG(VIPH_TIMEOUT_STAT);
86 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
89 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
134 OUTREG(RADEON_VIPH_TIMEOUT_STAT, INREG(RADEON_VIPH_TIMEOUT_STAT) & (0xffffff00 & ~RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
141 INREG(RADEON_VIPH_REG_DATA);
149 tmp=INREG(RADEON_VIPH_TIMEOUT_STAT);
155 *buffer=(uint8_t)(INREG(RADEON_VIPH_REG_DAT
[all...]
H A Dradeon_driver.c290 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
291 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
292 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
326 CardTmp = INREG(RADEON_MEM_CNTL);
336 CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
345 CardTmp = INREG(RADEON_MPP_TB_CONFIG);
582 (void)INREG(RADEON_CLOCK_CNTL_DATA);
583 (void)INREG(RADEON_CRTC_GEN_CNTL);
606 save = INREG(RADEON_CLOCK_CNTL_INDEX);
609 tmp = INREG(RADEON_CLOCK_CNTL_DAT
[all...]
H A Dlegacy_output.c179 uint32_t fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
180 uint32_t fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
187 native_mode->PanelYRes = (INREG(RADEON_CRTC_V_TOTAL_DISP)>>16) + 1;
193 native_mode->PanelXRes = ((INREG(RADEON_CRTC_H_TOTAL_DISP)>>16) + 1) * 8;
307 INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
367 save->dac_cntl = INREG(RADEON_DAC_CNTL);
368 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
369 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
370 save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
371 save->disp_tv_out_cntl = INREG(RADEON_DISP_TV_OUT_CNT
[all...]
H A Dlegacy_crtc.c101 tmp = INREG(RADEON_DAC_CNTL2);
504 save->ovr_clr = INREG(RADEON_OVR_CLR);
505 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
506 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
507 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
508 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
509 save->viph_control = INREG(RADEON_VIPH_CONTROL);
510 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
511 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
512 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNT
[all...]
H A Dradeon_tv.c224 OUTREG(RADEON_TEST_DEBUG_MUX, (INREG(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
244 OUTREG(RADEON_TEST_DEBUG_MUX, INREG(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
263 tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL);
287 tmp = INREG(RADEON_TV_HOST_RD_WT_CNTL);
297 return INREG(RADEON_TV_HOST_READ_DATA);
524 save->tv_uv_adr = INREG(RADEON_TV_UV_ADR);
571 save->tv_crc_cntl = INREG(RADEON_TV_CRC_CNTL);
572 save->tv_frestart = INREG(RADEON_TV_FRESTART);
573 save->tv_hrestart = INREG(RADEON_TV_HRESTART);
574 save->tv_vrestart = INREG(RADEON_TV_VRESTAR
[all...]
H A Dradeon_macros.h65 #define INREG(addr) MMIO_IN32(RADEONMMIO, addr) macro
75 uint32_t tmp = INREG(addr); \
129 INREG(AVIVO_DC_LUT_30_COLOR); \
131 INREG(RADEON_PALETTE_30_DATA); \
145 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
148 OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
H A Dradeon_accel.c137 INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
142 (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
143 (unsigned int)INREG(RADEON_RBBM_STATUS));
167 INREG(R600_GRBM_STATUS) & R700_CMDFIFO_AVAIL_MASK;
170 INREG(R600_GRBM_STATUS) & R600_CMDFIFO_AVAIL_MASK;
175 (unsigned int)INREG(R600_GRBM_STATUS));
200 if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
206 (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
213 if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
219 (unsigned int)INREG(R300_DSTCACHE_CTLSTA
[all...]
/xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/
H A Daudio.c47 dword = INREG(reg); \
261 dword = INREG(AUD_VID_DID);
265 dword = INREG(AUD_RID);
271 dword = INREG(SDVOB);
278 dword = INREG(SDVOC);
285 dword = INREG(PORT_HOTPLUG_EN);
295 dword = INREG(VIDEO_DIP_CTL);
310 dword = INREG(AUD_CONFIG);
317 dword = INREG(AUD_DEBUG);
320 dword = INREG(AUD_SUBN_CN
[all...]
H A Dstatuspage.c55 hws_offset = INREG(HWS_PGA);
H A Dhotplug.c118 INREG(PORT_HOTPLUG_STAT);
122 printf("%5d: 0x%08x\n", i, INREG(PORT_HOTPLUG_STAT));
/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740_macros.h51 while (INREG(BITBLT_CONTROL) & BLTR_STATUS); \
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_debug.c334 Bool is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
340 if ((INREG(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
1392 igdng_snapshot[i].val = INREG(igdng_snapshot[i].reg);
1396 i830_snapshot[i].val = INREG(i830_snapshot[i].reg);
1409 uint32_t val = INREG(igdng_snapshot[i].reg);
1448 uint32_t val = INREG(i830_snapshot[i].reg);
1526 uint32_t val = INREG(igdng_snapshot[i].reg);
1565 uint32_t val = INREG(i830_snapshot[i].reg);
1596 fp = INREG(pipe == 0 ? FPA0 : FPB0);
1597 dpll = INREG(pip
[all...]
H A Di830_driver.c282 switch (INREG(PGETBL_CTL) & PGETBL_SIZE_MASK) {
302 FatalError("Unknown GTT size value: %08x\n", (int)INREG(PGETBL_CTL));
659 if ((INREG(SDVOB) & SDVO_DETECTED)) {
666 if ((INREG(SDVOB) & SDVO_DETECTED))
669 if ((INREG(SDVOC) & SDVO_DETECTED) &&
748 OUTREG(SWF0, INREG(SWF0) | (1 << 21));
751 OUTREG(SWF4, (INREG(SWF4) & ~((3 << 19) | (7 << 16))) |
1651 temp = INREG(LP_RING + RING_LEN);
1707 pI830->ring.head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
1708 pI830->ring.tail = INREG(LP_RIN
[all...]
H A Di830_crt.c44 temp = INREG(ADPA);
72 pI830->saveADPA = INREG(ADPA);
136 dpll_md = INREG(dpll_md_reg);
186 hotplug_en = INREG(PORT_HOTPLUG_EN);
211 temp = INREG(PORT_HOTPLUG_EN);
219 temp = INREG(PORT_HOTPLUG_STAT);
272 save_bclrpat = INREG(bclrpat_reg);
273 save_vtotal = INREG(vtotal_reg);
274 vblank = INREG(vblank_reg);
287 uint32_t pipeconf = INREG(pipeconf_re
[all...]
H A Di810_ring.h67 _head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK; \
68 _tail = INREG(LP_RING + RING_TAIL) & I830_TAIL_MASK; \
H A Di830_tv.c787 OUTREG(TV_CTL, INREG(TV_CTL) | TV_ENC_ENABLE);
792 OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
807 dev_priv->save_TV_H_CTL_1 = INREG(TV_H_CTL_1);
808 dev_priv->save_TV_H_CTL_2 = INREG(TV_H_CTL_2);
809 dev_priv->save_TV_H_CTL_3 = INREG(TV_H_CTL_3);
810 dev_priv->save_TV_V_CTL_1 = INREG(TV_V_CTL_1);
811 dev_priv->save_TV_V_CTL_2 = INREG(TV_V_CTL_2);
812 dev_priv->save_TV_V_CTL_3 = INREG(TV_V_CTL_3);
813 dev_priv->save_TV_V_CTL_4 = INREG(TV_V_CTL_4);
814 dev_priv->save_TV_V_CTL_5 = INREG(TV_V_CTL_
[all...]
H A Di965_video.c165 v = INREG(BRW_SVG_RDATA);
184 INREG(BRW_EU_ATT_1), INREG(BRW_EU_ATT_0),
185 INREG(BRW_EU_ATT_DATA_1), INREG(BRW_EU_ATT_DATA_0));
238 ctl = INREG(BRW_VF_CTL);
243 rdata = INREG(BRW_VF_RDATA);
250 ctl = INREG(BRW_VS_CTL);
255 rdata = INREG(BRW_VS_RDATA);
260 rdata = INREG(BRW_VS_RDAT
[all...]
H A Di830_hdmi.c109 temp = INREG(dev_priv->output_reg);
112 temp = INREG(dev_priv->output_reg);
125 dev_priv->save_SDVO = INREG(dev_priv->output_reg);
163 temp = INREG(PEG_BAND_GAP_DATA);
167 temp = INREG(PORT_HOTPLUG_EN);
196 if ((INREG(PORT_HOTPLUG_STAT) & bit) != 0)
300 temp = INREG(dev_priv->output_reg);
H A Di830_dvo.c95 OUTREG(dvo_reg, INREG(dvo_reg) | DVO_ENABLE);
100 OUTREG(dvo_reg, INREG(dvo_reg) & ~DVO_ENABLE);
116 pI830->saveDVOA = INREG(DVOA);
117 pI830->saveDVOB = INREG(DVOB);
118 pI830->saveDVOC = INREG(DVOC);
225 dvo = INREG(dvo_reg) & (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
236 OUTREG(dpll_reg, INREG(dpll_reg) | DPLL_DVO_HIGH_SPEED);
317 int pipe = !!(INREG(drv->dvo_reg) & SDVO_PIPE_B_SELECT);
354 uint32_t dvo = INREG(dvo_reg);
/xsrc/external/mit/xf86-video-imstt/dist/src/
H A Dimstt_accel.c48 while(INREG(IMSTT_SSTATUS) & 0x80);
49 while(INREG(IMSTT_SSTATUS) & 0x40);
88 while(INREG(IMSTT_SSTATUS) & 0x80);
102 while(INREG(IMSTT_SSTATUS) & 0x80);
103 while(INREG(IMSTT_SSTATUS) & 0x40);
180 while(INREG(IMSTT_SSTATUS) & 0x80);
181 while(INREG(IMSTT_SSTATUS) & 0x40);
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_ring.h67 _head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK; \
68 _tail = INREG(LP_RING + RING_TAIL) & I830_TAIL_MASK; \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_ring.h67 _head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK; \
68 _tail = INREG(LP_RING + RING_TAIL) & I830_TAIL_MASK; \
/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v_i2c.c85 reg = (INREG(DDC_REG));
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_driver.c374 return INREG(R128_CLOCK_CNTL_DATA);
385 return INREG(R128_PALETTE_DATA);
398 if (INREG(R128_GEN_INT_STATUS) & R128_VSYNC_INT) break;
932 pScrn->videoRam = INREG(R128_CONFIG_MEMSIZE) / 1024;
934 info->MemCntl = INREG(R128_MEM_CNTL);
935 info->BusCntl = INREG(R128_BUS_CNTL);
2294 tmp = INREG(R128_LVDS_GEN_CNTL);
2338 save->ovr_clr = INREG(R128_OVR_CLR);
2339 save->ovr_wid_left_right = INREG(R128_OVR_WID_LEFT_RIGHT);
2340 save->ovr_wid_top_bottom = INREG(R128_OVR_WID_TOP_BOTTO
[all...]

Completed in 28 milliseconds

1234