Searched refs:INT (Results 1 - 25 of 87) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/d3d10umd/
H A DDraw.h40 UINT StartIndexLocation, INT BaseVertexLocation);
48 INT BaseVertexLocation, UINT StartInstanceLocation);
H A DState.h100 INT LastEmittedQuerySeqNo;
101 INT LastFinishedQuerySeqNo;
391 INT SeqNo;
H A DDraw.cpp158 INT BaseVertexLocation) // IN
254 INT BaseVertexLocation, // IN
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_reg_type.c268 [BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
269 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
270 [BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
271 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
272 [BRW_REGISTER_TYPE_B] = { GFX10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
273 [BRW_REGISTER_TYPE_UB] = { GFX10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
281 [BRW_REGISTER_TYPE_D] = { GFX10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
282 [BRW_REGISTER_TYPE_UD] = { GFX10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
283 [BRW_REGISTER_TYPE_W] = { GFX10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
284 [BRW_REGISTER_TYPE_UW] = { GFX10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
[all...]
/xsrc/external/mit/xorg-server.old/dist/hw/xwin/glx/
H A Dwgl.tm22 INT,*,*, INT,*,*
/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/wgl/
H A Dstw_context.h51 DHGLRC stw_create_context_attribs(HDC hdc, INT iLayerPlane,
H A Dstw_pixelformat.c345 DrvDescribePixelFormat(HDC hdc, INT iPixelFormat, ULONG cjpfd,
376 DrvDescribeLayerPlane(HDC hdc, INT iPixelFormat, INT iLayerPlane,
385 DrvGetLayerPaletteEntries(HDC hdc, INT iLayerPlane, INT iStart,
386 INT cEntries, COLORREF *pcr)
394 DrvSetLayerPaletteEntries(HDC hdc, INT iLayerPlane, INT iStart,
395 INT cEntries, CONST COLORREF *pcr)
403 DrvRealizeLayerPalette(HDC hdc, INT iLayerPlan
[all...]
H A Dstw_icd.h526 INT iLayerPlane );
539 INT iPixelFormat,
540 INT iLayerPlane,
547 INT iPixelFormat,
554 INT iLayerPlane,
555 INT iStart,
556 INT cEntries,
569 INT iLayerPlane,
578 INT nProcs,
590 INT iLayerPlan
[all...]
H A Dstw_device.c227 DrvSetCallbackProcs(INT nProcs, PROC *pProcs)
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/wgl/
H A Dstw_context.h52 struct stw_context *stw_create_context_attribs(HDC hdc, INT iLayerPlane,
H A Dstw_pixelformat.c377 DrvDescribePixelFormat(HDC hdc, INT iPixelFormat, ULONG cjpfd,
406 DrvDescribeLayerPlane(HDC hdc, INT iPixelFormat, INT iLayerPlane,
415 DrvGetLayerPaletteEntries(HDC hdc, INT iLayerPlane, INT iStart,
416 INT cEntries, COLORREF *pcr)
424 DrvSetLayerPaletteEntries(HDC hdc, INT iLayerPlane, INT iStart,
425 INT cEntries, CONST COLORREF *pcr)
433 DrvRealizeLayerPalette(HDC hdc, INT iLayerPlan
[all...]
H A Dgldrv.h482 VOID APIENTRY DrvSetCallbackProcs(INT, PROC *); // See WGLCALLBACKS for expected order/count per OS.
483 BOOL APIENTRY DrvDescribeLayerPlane(HDC, INT, INT, UINT,
485 INT APIENTRY DrvSetLayerPaletteEntries(HDC, INT, INT, INT,
487 INT APIENTRY DrvGetLayerPaletteEntries(HDC, INT, INT, IN
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_reg_type.c180 [BRW_REGISTER_TYPE_D] = { GEN10_ALIGN1_3SRC_REG_TYPE_D, E(INT) },
181 [BRW_REGISTER_TYPE_UD] = { GEN10_ALIGN1_3SRC_REG_TYPE_UD, E(INT) },
182 [BRW_REGISTER_TYPE_W] = { GEN10_ALIGN1_3SRC_REG_TYPE_W, E(INT) },
183 [BRW_REGISTER_TYPE_UW] = { GEN10_ALIGN1_3SRC_REG_TYPE_UW, E(INT) },
184 [BRW_REGISTER_TYPE_B] = { GEN10_ALIGN1_3SRC_REG_TYPE_B, E(INT) },
185 [BRW_REGISTER_TYPE_UB] = { GEN10_ALIGN1_3SRC_REG_TYPE_UB, E(INT) },
/xsrc/external/mit/MesaLib.old/dist/include/D3D9/
H A Dd3d9caps.h291 INT DynamicFlowControlDepth;
292 INT NumTemps;
293 INT StaticFlowControlDepth;
298 INT DynamicFlowControlDepth;
299 INT NumTemps;
300 INT StaticFlowControlDepth;
301 INT NumInstructionSlots;
/xsrc/external/mit/MesaLib/dist/include/D3D9/
H A Dd3d9caps.h291 INT DynamicFlowControlDepth;
292 INT NumTemps;
293 INT StaticFlowControlDepth;
298 INT DynamicFlowControlDepth;
299 INT NumTemps;
300 INT StaticFlowControlDepth;
301 INT NumInstructionSlots;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_format.c146 V_(R32_SNORM, INT, NONE),
147 V_(R32_SINT, INT, NONE),
150 V_(R32_SSCALED, INT, NONE),
204 V_(R32G32_SNORM, INT, NONE),
206 V_(R32G32_SINT, INT, NONE),
208 V_(R32G32_SSCALED, INT, NONE),
214 V_(R32G32B32_SNORM, INT, NONE),
216 V_(R32G32B32_SINT, INT, NONE),
218 V_(R32G32B32_SSCALED, INT, NONE),
224 V_(R32G32B32A32_SNORM, INT, NON
[all...]
/xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
H A Ds_expression.h158 s_pattern(s_int *&s) : p_int(&s), type(INT) { }
172 enum { EXPR, LIST, SYMBOL, NUMBER, INT, STRING } type; enumerator in enum:s_pattern::__anone1bf381f0203
/xsrc/external/mit/MesaLib.old/dist/src/compiler/glsl/
H A Ds_expression.h158 s_pattern(s_int *&s) : p_int(&s), type(INT) { }
172 enum { EXPR, LIST, SYMBOL, NUMBER, INT, STRING } type; enumerator in enum:s_pattern::__anon77d16b4c0203
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_format.c134 V_(R32_SNORM, INT, NONE),
138 V_(R32_SSCALED, INT, NONE),
196 V_(R32G32_SNORM, INT, NONE),
200 V_(R32G32_SSCALED, INT, NONE),
206 V_(R32G32B32_SNORM, INT, NONE),
210 V_(R32G32B32_SSCALED, INT, NONE),
216 V_(R32G32B32A32_SNORM, INT, NONE),
220 V_(R32G32B32A32_SSCALED, INT, NONE),
/xsrc/external/mit/libxcb/dist/tools/
H A Dapi_conv.pl64 return "int$1_t" if /^INT(8|16|32)$/;
/xsrc/external/mit/MesaLib/dist/src/gallium/tools/trace/
H A Dtracediff.sh99 trap do_cleanup HUP INT TERM
/xsrc/external/mit/xterm/dist/vttests/
H A Dresize.pl109 $SIG{INT} = \&catch_zap;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/state_trackers/nine/
H A Ddevice9ex.h85 INT *pPriority );
89 INT Priority );
/xsrc/external/mit/MesaLib/dist/src/gallium/frontends/nine/
H A Ddevice9ex.h85 INT *pPriority );
89 INT Priority );
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/modes/
H A Dxf86DisplayIDModes.c184 #define INT 2 macro
204 { 1024, 768, 43, INT },
291 if (d->f == INT)

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