| /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/ |
| H A D | ir3_array_to_ssa.c | 126 src_reg = ir3_src_create(phi, INVALID_REG, flags | IR3_REG_SSA);
293 reg->flags |= IR3_REG_SSA;
306 reg->flags |= IR3_REG_SSA;
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| H A D | ir3_cse.c | 133 if ((src->flags & IR3_REG_SSA) && src->def &&
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| H A D | ir3_ra.h | 98 return (reg->flags & IR3_REG_SSA) && reg->def && def_is_gpr(reg->def);
104 return (reg->flags & IR3_REG_SSA) && def_is_gpr(reg) &&
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| H A D | ir3_merge_regs.c | 370 if (!(pcopy->srcs[i]->flags & IR3_REG_SSA))
390 if (!(collect->srcs[i]->flags & IR3_REG_SSA))
413 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) &&
433 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) &&
459 if ((phi->srcs[pred_idx]->flags & IR3_REG_SSA) &&
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| H A D | ir3_context.c | 521 cond->dsts[0]->flags &= ~IR3_REG_SSA;
654 IR3_REG_SSA | IR3_REG_ARRAY | flags | COND(address, IR3_REG_RELATIV));
660 ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->dsts[0];
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| H A D | ir3_print.c | 263 if (reg->flags & IR3_REG_SSA) {
274 } else if (reg->flags & IR3_REG_SSA) {
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| H A D | ir3_validate.c | 78 if (!(reg->flags & IR3_REG_SSA) || !reg->def)
152 if (reg->flags & IR3_REG_SSA)
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| H A D | ir3_cp.c | 137 *dstflags &= ~IR3_REG_SSA;
138 *dstflags |= srcflags & IR3_REG_SSA;
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| H A D | ir3_ra.c | 1331 entry->interval->interval.reg->flags & ~IR3_REG_SSA);
1341 entry->interval->interval.reg->flags & ~IR3_REG_SSA);
1778 ir3_dst_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA);
1788 ir3_src_create(pcopy, INVALID_REG, reg->flags & ~IR3_REG_SSA);
2296 instr->dsts[i]->flags &= ~IR3_REG_SSA;
2309 instr->srcs[i]->flags &= ~IR3_REG_SSA;
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| H A D | ir3.h | 132 IR3_REG_SSA = 0x4000, /* 'def' is ptr to assigning destination */ enumerator in enum:ir3_register::__anon3fdcb7e60103
194 /* For IR3_REG_SSA, src registers contain ptr back to assigning
1166 if ((reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) && reg->def)
1709 reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags);
1718 struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA);
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| H A D | ir3_spill.c | 678 IR3_REG_CONST | IR3_REG_SSA |
1382 assert(new_val->flags & IR3_REG_SSA);
1666 if (!(interval->dst.flags & IR3_REG_SSA) ||
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| H A D | ir3.c | 816 if (instr->srcs[n]->flags & IR3_REG_SSA) {
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| H A D | ir3_sched.c | 1044 if (!(instr->dsts[0]->flags & IR3_REG_SSA))
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| H A D | ir3_compiler_nir.c | 2040 cond->dsts[0]->flags &= ~IR3_REG_SSA;
3205 cond->dsts[0]->flags &= ~IR3_REG_SSA;
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| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/ |
| H A D | ir3_group.c | 67 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in;
212 ir3_reg_create(instr, 0, IR3_REG_SSA); /* dummy dst */
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| H A D | ir3_context.c | 345 ir3_reg_create(collect, 0, IR3_REG_SSA | flags)->instr = elem;
371 ir3_reg_create(split, 0, IR3_REG_SSA | flags);
372 ir3_reg_create(split, 0, IR3_REG_SSA | flags)->instr = src;
611 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src;
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| H A D | ir3.h | 96 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */ enumerator in enum:ir3_register::__anond9a07c730103
120 /* For IR3_REG_SSA, src registers contain ptr back to assigning
779 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) {
1097 reg = ir3_reg_create(instr, 0, IR3_REG_SSA | flags);
1331 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
1336 reg = ir3_reg_create(sam, 0, IR3_REG_SSA);
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| H A D | ir3_print.c | 117 } else if (reg->flags & IR3_REG_SSA) {
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| H A D | ir3_cp.c | 253 *dstflags &= ~IR3_REG_SSA;
254 *dstflags |= srcflags & IR3_REG_SSA;
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| H A D | ir3_ra.c | 1045 reg->flags &= ~IR3_REG_SSA;
1060 reg->flags &= ~IR3_REG_SSA;
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| H A D | ir3_compiler_nir.c | 55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/ |
| H A D | ir3-notes.rst | 44 The ir3 IR maps quite directly to the hardware, in that instruction opcodes map directly to hardware opcodes, and that dst/src register(s) map directly to the hardware dst/src register(s). But there are a few extensions, in the form of meta_ instructions. And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is set and ``reg->instr`` points to the source instruction which produced that value. So, for example, the following TGSI shader:
113 If ``IR3_REG_SSA`` is set on a src register, the actual register
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| /xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/ |
| H A D | ir3-notes.rst | 44 The ir3 IR maps quite directly to the hardware, in that instruction opcodes map directly to hardware opcodes, and that dst/src register(s) map directly to the hardware dst/src register(s). But there are a few extensions, in the form of meta_ instructions. And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is set and ``reg->instr`` points to the source instruction which produced that value. So, for example, the following TGSI shader:
113 If ``IR3_REG_SSA`` is set on a src register, the actual register
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