| /xsrc/external/mit/MesaLib/dist/src/compiler/isaspec/ |
| H A D | decode.py | 25 from isa import ISA
299 isa = ISA(xml)
|
| H A D | encode.py | 25 from isa import ISA, BitSetDerivedField, BitSetAssertField
615 isa = ISA(xml)
|
| H A D | isa.py | 383 class ISA(object): class in inherits:object
|
| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README-ISA.md | 1 # Unofficial GCN/RDNA ISA reference errata
5 The Vega ISA reference writes its behaviour as:
26 Both the RDNA, Vega and GCN3 ISA references write that these instructions don't write
31 The Vega ISA reference writes its behaviour as:
49 All versions of the ISA document are vague about it, but after some trial and
61 The Vega ISA references doesn't say this (or doesn't make it clear), but
64 The RDNA ISA doesn't mention SMEM stores at all, but they seem to be supported
70 RDNA ISA: same as the SMEM stores, the ISA pretends they don't exist, but they
90 The `image_atomic_{swap,cmpswap,add,sub}` opcodes in the GCN3 ISA referenc
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/drivers/freedreno/ |
| H A D | ir3-notes.rst | 4 Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with adreno a3xx. The same shader ISA is present, with some small differences, in adreno a4xx.
6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or nops). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
17 For additional documentation about the hardware, see wiki: `a3xx ISA
386 In this stage, simple if/else blocks are flattened into a single block with ``phi`` nodes converted into ``sel`` instructions. The a3xx ISA has very few predicated instructions, and we would prefer not to use branches for simple if/else.
|
| /xsrc/external/mit/MesaLib/dist/docs/drivers/freedreno/ |
| H A D | ir3-notes.rst | 4 Some notes about ir3, the compiler and machine-specific IR for the shader ISA introduced with adreno a3xx. The same shader ISA is present, with some small differences, in adreno a4xx.
6 Compared to the previous generation a2xx ISA (ir2), the a3xx ISA is a "simple" scalar instruction set. However, the compiler is responsible, in most cases, to schedule the instructions. The hardware does not try to hide the shader core pipeline stages. For a common example, a common (cat2) ALU instruction takes four cycles, so a subsequent cat2 instruction which uses the result must have three intervening instructions (or NOPs). When operating on vec4's, typically the corresponding scalar instructions for operating on the remaining three components could typically fit. Although that results in a lot of edge cases where things fall over, like:
17 For additional documentation about the hardware, see wiki: `a3xx ISA
357 In this stage, simple if/else blocks are flattened into a single block with ``phi`` nodes converted into ``sel`` instructions. The a3xx ISA has very few predicated instructions, and we would prefer not to use branches for simple if/else.
|
| H A D | isaspec.rst | 1 ISASPEC - XML Based ISA Specification
11 Benefits of a formal ISA description, compared to hand-coded assemblers
35 design around the idea of disassembly based on a formal ISA description).
|
| /xsrc/external/mit/xf86-video-trident/dist/ |
| H A D | configure.ac | 72 [AC_DEFINE(HAVE_ISA, 1, [Have ISA support])],
|
| /xsrc/external/mit/xf86-video-vboxvideo/dist/ |
| H A D | configure.ac | 76 [AC_DEFINE(HAVE_ISA, 1, [Have ISA support])],
|
| /xsrc/external/mit/xf86-video-vesa/dist/ |
| H A D | configure.ac | 71 [AC_DEFINE(HAVE_ISA, 1, [Have ISA support])],
|
| /xsrc/external/mit/xf86-video-neomagic/dist/ |
| H A D | configure.ac | 61 [AC_DEFINE(HAVE_ISA, 1, [Have ISA support])],
|
| /xsrc/external/mit/xf86-video-chips/dist/ |
| H A D | configure.ac | 99 [AC_DEFINE(HAVE_ISA, 1, [Have ISA support])],
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/ |
| H A D | tgsi.rst | 49 Core ISA
821 Compute ISA
989 Integer ISA
1522 Bitwise ISA
1593 Geometry ISA
1611 GLSL ISA
1740 Interpolation ISA
1765 Double ISA
2018 64-bit Integer ISA
|
| H A D | screen.rst | 634 * ``PIPE_SHADER_CAP_SCALAR_ISA``: Whether the ISA is a scalar one.
|
| /xsrc/external/mit/MesaLib/dist/docs/gallium/ |
| H A D | tgsi.rst | 52 Core ISA
847 Compute ISA
1023 Integer ISA
1556 Bitwise ISA
1627 Geometry ISA
1645 GLSL ISA
1774 Interpolation ISA
1799 Double ISA
2052 64-bit Integer ISA
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/sb/ |
| H A D | notes.markdown | 319 equal to the number of source operands for the ISA instruction.
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sb/ |
| H A D | notes.markdown | 319 equal to the number of source operands for the ISA instruction.
|
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 21.0.0.rst | 333 - pan/bi: Mark message types in ISA.xml
335 - pan/bi: Add staging register counts to ISA.xml
338 - pan/bi: Add explicit meson dependency on the ISA helpers
340 - pan/bi: Add helpers for manipulating the ISA
2334 - android: pan/bi: Add explicit dependency on the ISA helpers
|
| H A D | 21.1.0.rst | 414 - pan/bi: Annotate ISA.xml with 'last' parameter
3695 - android: freedreno/hw/isa: Add description of ir3 ISA
4847 - freedreno/hw: Add isaspec mechanism for documenting/defining an ISA
4848 - freedreno/hw/isa: Add description of ir3 ISA
|
| H A D | 7.10.rst | 1320 - i965: Add support for gen6 DO/WHILE ISA emit.
1321 - i965: Add support for gen6 BREAK ISA emit.
|
| H A D | 20.3.0.rst | 607 - pan/bi: Add ISA parser
4498 - aco: Move README to README-ISA
4499 - aco: Fixup markdown formatting of the README-ISA.
|
| H A D | 21.3.0.rst | 298 - pan/va: Add initial ISA.xml for Valhall
299 - pan/va: Add ISA.xml parser and support code
|
| H A D | 21.2.0.rst | 615 - panfrost/ci: Split rules by ISA
5013 - aco: Add note about v_alignbyte in the ISA README.
|
| /xsrc/external/mit/MesaLib/dist/ |
| H A D | .pick_status.json | 1705 "description": "pan/mdg: Clarify some ISA unknowns",
23368 "description": "radv/sqtt: always dump pipelines and shaders ISA",
[all...] |