Searched refs:KB (Results 1 - 25 of 28) sorted by relevance
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/reg_dumper/ |
| H A D | gtt.c | 39 #define INGTT(offset) (*(volatile uint32_t *)(gtt + (offset) / (KB(4) / 4)))
58 gtt = (unsigned char *)(pI830->mmio + KB(512));
75 for (start = 0; start < aper_size; start += KB(4)) {
82 for (end = start + KB(4); end < aper_size; end += KB(4)) {
92 start, end - KB(4),
93 start_pte, start_pte + (end - start) - KB(4));
94 start = end - KB(4);
99 for (end = start + KB(4); end < aper_size; end += KB(
[all...] |
| /xsrc/external/mit/xf86-video-intel/dist/src/uxa/ |
| H A D | common.h | 55 #define KB(x) ((x) * 1024) macro
56 #define MB(x) ((x) * KB(1024))
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| H A D | intel_memory.c | 108 start = KB(512);
149 limit = KB(8);
151 limit = KB(8);
153 limit = KB(16);
155 limit = KB(32);
157 limit = KB(32);
210 if (pitch > KB(8))
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| H A D | intel_uxa.h | 212 if (pitch > KB(32)) {
220 /* For pre-965 chip only, as they have 8KB limit for 3D */
225 if (pitch > KB(8)) {
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| H A D | intel_uxa.c | 640 intel_pixmap_pitch(pixmap) >= KB(32)) {
643 __FUNCTION__, intel_pixmap_pitch(pixmap), stride, KB(32), tile_width);
1040 if (size > intel->max_bo_size || stride >= KB(32))
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/ |
| H A D | common.h | 55 #define KB(x) ((x) * 1024) macro
56 #define MB(x) ((x) * KB(1024))
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| H A D | intel_memory.c | 108 start = KB(512);
149 limit = KB(8);
151 limit = KB(8);
153 limit = KB(16);
155 limit = KB(32);
157 limit = KB(32);
210 if (pitch > KB(8))
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| H A D | intel_uxa.h | 212 if (pitch > KB(32)) {
220 /* For pre-965 chip only, as they have 8KB limit for 3D */
225 if (pitch > KB(8)) {
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| H A D | intel_uxa.c | 615 intel_pixmap_pitch(pixmap) >= KB(32)) {
618 __FUNCTION__, intel_pixmap_pitch(pixmap), stride, KB(32), tile_width);
1015 if (size > intel->max_bo_size || stride >= KB(32))
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| /xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/ |
| H A D | i810_common.h | 50 #define KB(x) ((x) * 1024) macro
51 #define MB(x) ((x) * KB(1024))
140 #define GTT_PAGE_SIZE KB(4)
141 #define PRIMARY_RINGBUFFER_SIZE KB(128)
142 #define MIN_SCRATCH_BUFFER_SIZE KB(16)
143 #define MAX_SCRATCH_BUFFER_SIZE KB(64)
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| H A D | i810_memory.c | 287 case KB(512):
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/ |
| H A D | i810_common.h | 50 #define KB(x) ((x) * 1024) macro
51 #define MB(x) ((x) * KB(1024))
140 #define GTT_PAGE_SIZE KB(4)
141 #define PRIMARY_RINGBUFFER_SIZE KB(128)
142 #define MIN_SCRATCH_BUFFER_SIZE KB(16)
143 #define MAX_SCRATCH_BUFFER_SIZE KB(64)
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| H A D | i810_memory.c | 287 case KB(512):
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| /xsrc/external/mit/xf86-video-intel-old/dist/src/ |
| H A D | common.h | 68 #define KB(x) ((x) * 1024) macro
69 #define MB(x) ((x) * KB(1024))
385 #define GTT_PAGE_SIZE KB(4)
390 #define PRIMARY_RINGBUFFER_SIZE KB(128)
391 #define MIN_SCRATCH_BUFFER_SIZE KB(16)
392 #define MAX_SCRATCH_BUFFER_SIZE KB(64)
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| H A D | i830_memory.c | 126 start = KB(512);
176 int limit = KB(32);
181 limit = KB(8);
184 limit = KB(8);
187 limit = KB(16);
1021 if (pitch / 512 * 512 == pitch && pitch <= KB(128))
1039 case KB(1):
1040 case KB(2):
1041 case KB(4):
1042 case KB(
[all...] |
| H A D | i830_hwmc.c | 147 int size = KB(64);
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| H A D | i830_driver.c | 324 /* The stolen memory has the GTT at the top, and the 4KB popup below that.
336 memsize = MB(1) - KB(range);
339 memsize = MB(4) - KB(range);
342 memsize = MB(8) - KB(range);
345 memsize = MB(16) - KB(range);
348 memsize = MB(32) - KB(range);
352 memsize = MB(48) - KB(range);
356 memsize = MB(64) - KB(range);
360 memsize = MB(128) - KB(range);
364 memsize = MB(256) - KB(rang
[all...] |
| H A D | i810_memory.c | 286 case KB(512):
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| H A D | i830.h | 877 if (pitch > KB(32)) I830FALLBACK("pitch exceeds 2d limit 32K\n");\
880 /* For pre-965 chip only, as they have 8KB limit for 3D */
883 if (pitch > KB(8)) I830FALLBACK("pitch exceeds 3d limit 8K\n");\
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| H A D | i830_display.c | 1912 int align = KB(4), size;
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| /xsrc/external/mit/MesaLib/dist/docs/isl/ |
| H A D | tiling.rst | 25 each of which is 4KB of memory. Within each tile, the pixels are laid out like
36 which is 4KB of memory. Within a tile, each 64B cache line corresponds to 4x4
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| H A D | ccs.rst | 73 of bytes within a 4KB page whereas the negative bits represent the address of
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/ |
| H A D | screen.rst | 400 most 64KB.
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| /xsrc/external/mit/MesaLib/dist/docs/gallium/ |
| H A D | screen.rst | 429 most 64KB.
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 20.1.0.rst | 845 - intel/gen12+: Reserve 4KB of URB space per bank for Compute Engine
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