Searched refs:L3 (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.7.rst131 - intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
132 - anv: invalidate L3 read only cache when VF cache is invalidated
133 - iris: invalidate L3 read only cache when VF cache is invalidated
H A D20.0.6.rst93 - intel/devinfo: Compute the correct L3$ size for Gen12
H A D20.3.3.rst101 - util: add AMD CPU family enums and enable L3 cache pinning on Zen3
H A D21.0.2.rst63 - util: rework AMD cpu L3 cache affinity code.
H A D17.1.4.rst130 - anv: Fix L3 cache programming on Bay Trail
H A D17.2.6.rst135 - i965: Make L3 configuration atom listen for TCS/TES program updates.
H A D20.1.0.rst2332 - iris: Set SLMEnable based on the L3$ config
2333 - iris: Store the L3$ configs in the screen
2334 - iris: Use the URB size from the L3$ config
2503 - intel/devinfo: Compute the correct L3$ size for Gen12
3124 - gallium/u_threaded: call the driver to pin threads to L3 immediately
H A D21.1.0.rst1602 - st/glthread: allow for invalid L3 cache id.
1603 - util: rework AMD cpu L3 cache affinity code.
2742 - genxml: Make 1-bit L3$ config register fields bool on Gen7
3185 - anv: move L3 config emission to genX_state.c
3186 - anv: move L3 initialization to device init on Gen11+
3654 - util: fix (re-enable) L3 cache pinning
H A D20.0.0.rst1754 - iris: Set SLMEnable based on the L3$ config
1755 - iris: Store the L3$ configs in the screen
1756 - iris: Use the URB size from the L3$ config
H A D19.0.0.rst327 - i965/icl: Fix L3 configurations
1723 - st/mesa: disable L3 thread pinning
H A D20.2.0.rst811 - intel/l3: Add DG1 L3 configuration
2853 - iris/l3: Enable L3 full way allocation when L3 config is NULL
2854 - anv: Set L3 full way allocation at context init if L3 cfg is NULL
H A D19.1.0.rst2103 - iris: Configure the L3$ on the compute context
2346 - iris: Emit default L3 config for the render pipeline
3388 - iris: Use full ways for L3 cache setup on Icelake.
H A D21.2.0.rst2412 - intel: add L3 Bypass Disable to gen xml
2413 - iris: Cache VB/IB in L3$ for Gen12
2420 - anv: Cache VB/IB in L3$ for Gfx12
3421 - util: fix (re-enable) L3 cache pinning
H A D20.3.0.rst3549 - st/mesa: remove random L3 pinning heuristic for glthread
3552 - util: completely rewrite and do AMD Zen L3 cache pinning correctly
3553 - glthread: pin driver threads to the same L3 as the main thread regularly
H A D21.0.0.rst2275 - util: add AMD CPU family enums and enable L3 cache pinning on Zen3
2280 - st/mesa: simplify checking whether to pin threads to L3
H A D19.3.0.rst463 - intel/gen12: Add L3 configurations
H A D21.3.0.rst493 - intel/dg2: Add L3 configuration
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ddc/
H A Dedid.h117 #define L3 _L3(GET_ARRAY(V_MANUFACTURER)) macro
H A Dinterpret_edid.c347 r->name[2] = L3;
/xsrc/external/mit/xorg-server/dist/hw/xfree86/ddc/
H A Dedid.h116 #define L3 _L3(GET_ARRAY(V_MANUFACTURER)) macro
H A Dinterpret_edid.c445 r->name[2] = L3;
/xsrc/external/mit/MesaLib/dist/docs/
H A Denvvars.rst278 emit messages about the new L3 state during transitions
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json4288 "description": "iris: invalidate L3 read only cache when VF cache is invalidated",
4297 "description": "anv: invalidate L3 read only cache when VF cache is invalidated",
4306 "description": "intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation",
14656 "description": "intel/devinfo: Adjust L3 banks for DG2",
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