Searched refs:LS (Results 1 - 12 of 12) sorted by relevance
| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 17.1.9.rst | 52 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
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| H A D | 17.2.2.rst | 104 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
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| H A D | 11.0.3.rst | 119 - radeonsi: don't forget to update scratch relocations for LS, HS, ES
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| H A D | 20.3.5.rst | 258 - radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
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| H A D | 20.1.0.rst | 3523 - aco: fix instruction encoding for LS VGPR init bug workaround
3524 - aco: fix operand order for LS VGPR init bug workaround
4178 - aco: Fix LS VGPR init bug on affected hardware.
4214 - aco: When LS and HS invocations are the same, pass LS outputs in
4216 - aco: Don't store LS VS outputs to LDS when TCS doesn't need them.
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| H A D | 21.0.0.rst | 2285 - radeonsi: fix hang caused by for loop with exec=0 in LS and ES
3098 - radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
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| H A D | 20.0.0.rst | 3044 - radv: hardcode the number of waves for the GFX6 LS-HS bug
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| H A D | 21.1.0.rst | 5059 - radv,aco: fix shifting input VGPRs for the LS VGPR init bug on GFX9
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | README.md | 134 * LS = Local Shader (merged into HS on GFX9+), only runs SW VS when tessellation is used
172 * LS and HS share the same LDS space, so LS can store its output to LDS, where HS can read it
176 | GFX6-8 HW stages: | LS | HS | ES | GS | VS | PS | ACO terminology |
185 * HW LS and HS stages are merged, and the merged shader still uses LDS in the same way as before
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| H A D | aco_instruction_selection_setup.cpp | 860 hw_stage = HWStage::LS; /* GFX6-8: VS is a Local Shader, when tessellation is used */
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| H A D | aco_ir.h | 1941 LS, /* Local shader: pre-TCS (VS) on GFX6-8. Combined into HS on GFX9 (and GFX10/legacy). */ enumerator in enum:aco::HWStage
1991 static constexpr Stage vertex_ls(HWStage::LS, SWStage::VS); /* vertex before tesselation control */
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| H A D | aco_instruction_selection.cpp | 7073 bool shared_storage_used = ctx->stage.hw == HWStage::CS || ctx->stage.hw == HWStage::LS ||
8188 if (ctx->stage.hw == HWStage::LS || ctx->stage.hw == HWStage::HS) {
11287 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
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