Searched refs:MCP_SETN0CTL (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Dvid_rdcl.c2497 hsync_active_base = MCP_SETN0CTL;
2502 vsync_inactive_base = MCP_SETN0CTL;
2506 vsync_active_base = MCP_SETN0CTL;
H A Dgfx_regs.h1320 #define MCP_SETN0CTL 0x0048 macro
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Dvid_rdcl.c2485 hsync_active_base = MCP_SETN0CTL;
2490 vsync_inactive_base = MCP_SETN0CTL;
2495 vsync_active_base = MCP_SETN0CTL;
H A Dgfx_regs.h1240 #define MCP_SETN0CTL 0x0048 macro

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