Searched refs:MDC_DV_CTL (Results 1 - 6 of 6) sorted by relevance

/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Ddisp_gu2.c520 temp = READ_REG32(MDC_DV_CTL);
521 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);
1346 temp = READ_REG32(MDC_DV_CTL);
1347 WRITE_REG32(MDC_DV_CTL, temp | 0x00000001);
H A Dgfx_regs.h969 #define MDC_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ macro
1126 /* MDC_DV_CTL BIT DEFINITIONS */
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Ddisp_gu2.c280 temp = READ_REG32(MDC_DV_CTL);
281 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);
1051 temp = READ_REG32(MDC_DV_CTL);
1052 WRITE_REG32(MDC_DV_CTL, temp | 0x00000001);
H A Dgfx_regs.h881 #define MDC_DV_CTL 0x00000088 /* Dirty-Valid Control */ macro
1039 /* MDC_DV_CTL BIT DEFINITIONS */
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_gx2_driver.c1146 Gal_read_register(GAL_REG, MDC_DV_CTL, &temp, 4);
1148 Gal_write_register(GAL_REG, MDC_DV_CTL, temp, 4);
1150 temp = READ_REG32(MDC_DV_CTL);
1151 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);
/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dgx_driver.c822 temp = READ_REG32(MDC_DV_CTL);
823 WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);

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