| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/tests/ |
| H A D | test_insert_nops.cpp | 37 aco_opcode::image_sample, Format::MIMG, 3 + addrs, 1)};
73 /* no nop needed because the MIMG is not NSA */
130 /* no nop needed because the MIMG is not NSA */
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| H A D | test_hard_clause.cpp | 71 aco_opcode::image_sample, Format::MIMG, 5, 1)};
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| /xsrc/external/mit/MesaLib/dist/src/amd/compiler/ |
| H A D | aco_opt_value_numbering.cpp | 104 case Format::MIMG: return hash_murmur_32<MIMG_instruction>(instr);
258 case Format::MIMG: {
340 case Format::MIMG:
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| H A D | README-ISA.md | 88 ## MIMG opcodes on GFX8/GCN3
280 "MIMG-NSA in a hard clause has unpredictable results on GFX10.1"
284 NSA MIMG instructions should be limited to 3 dwords before GFX10.3 to avoid
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| H A D | aco_insert_waitcnt.cpp | 675 case Format::MIMG:
687 if (ctx.chip_class == GFX6 && instr->format != Format::MIMG && instr->operands.size() == 4) {
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| H A D | aco_opcodes.py | 63 MIMG = 11 variable in class:Format
118 elif self == Format.MIMG:
1407 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1409 opcode("image_msaa_load", -1, -1, 0x80, Format.MIMG, InstrClass.VMem) #GFX10.3+
1433 opcode(name, gfx7, gfx89, gfx7, Format.MIMG, InstrClass.VMem, is_atomic = True)
1479 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1512 opcode(name, code, code, code, Format.MIMG, InstrClass.VMem)
1514 opcode("image_bvh64_intersect_ray", -1, -1, 231, Format.MIMG, InstrClass.VMem)
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| H A D | aco_ir.cpp | 174 case Format::MIMG: return instr->mimg().sync;
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| H A D | aco_print_ir.cpp | 389 case Format::MIMG: {
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| H A D | aco_register_allocation.cpp | 1473 unsigned first_operand = vec->format == Format::MIMG ? 3 : 0;
1483 if (vec->format != Format::MIMG || is_mimg_vaddr_intact(ctx, reg_file, vec)) {
1498 /* return if MIMG vaddr components don't remain vector-aligned */
1499 if (vec->format == Format::MIMG)
2301 } else if (instr->format == Format::MIMG && instr->operands.size() > 4) {
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| H A D | aco_ir.h | 85 MIMG = 11, enumerator in enum:aco::Format
1141 constexpr bool isMIMG() const noexcept { return format == Format::MIMG; }
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| H A D | aco_assembler.cpp | 452 case Format::MIMG: {
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| H A D | aco_validate.cpp | 557 case Format::MIMG: {
558 check(instr->operands.size() >= 4, "MIMG instructions must have at least 4 operands",
562 "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
565 "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
572 "MIMG operands[2] (VDATA) must be the same as definitions[0] for atomics and "
582 "MIMG operands[3] (VADDR) must be VGPR", instr.get());
584 check(instr->operands[i].regClass() == v1, "MIMG VADDR must be v1 if NSA is used",
591 "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
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| H A D | aco_instruction_selection.cpp | 5989 create_instruction<MIMG_instruction>(op, Format::MIMG, 3 + coords.size(), dst.isTemp())};
9593 /* gather MIMG address components */
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| /xsrc/external/mit/MesaLib/dist/docs/relnotes/ |
| H A D | 21.0.0.rst | 2790 - aco: move MIMG VDATA to its own operand
3070 - aco: fix inserting expcnt for MIMG on GFX6
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| H A D | 21.1.0.rst | 4710 - aco: add affinity for non-sequential MIMG operands
4789 - aco: fix NSA MIMG followed by MUBUF/MTBUF
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| H A D | 21.2.0.rst | 4834 - aco: fix emitting d16 for MIMG instructions on GFX9+
4835 - aco: fix emitting a16 for MIMG instructions on GFX10+
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| H A D | 19.3.0.rst | 3289 - aco: Support GFX10 MIMG and GFX9 D16 in aco_assembler.
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| H A D | 20.0.0.rst | 773 - aco: simplify gathering of MIMG address components
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| H A D | 21.3.0.rst | 974 - aco/ra: don't allocate vector space for MIMG NSA operands
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