Searched refs:MISC_OUTPUT_REG_WRITE_PORT (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/xf86-video-xgi/dist/src/
H A Dxgi.h923 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 macro
H A Dvb_def.h38 #define MISC_OUTPUT_REG_WRITE_PORT 0x0012 macro
H A Dvb_init.c665 USHORT XGINew_2ndP3C2 = BaseAddr2nd + MISC_OUTPUT_REG_WRITE_PORT ;
H A Dvb_setmode.c4528 USHORT XGINew_2ndP3C2 = BaseAddr2nd + MISC_OUTPUT_REG_WRITE_PORT;

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