Searched refs:MI_INVALIDATE_MAP_CACHE (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_reg.h13 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
H A Dgen2_render.c711 BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
3481 BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
H A Dgen3_render.c2032 OUT_BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_reg.h13 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
H A Dgen2_render.c696 BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
3172 BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
H A Dgen3_render.c2008 OUT_BATCH(MI_FLUSH | MI_INVALIDATE_MAP_CACHE);
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_accel.c153 int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
H A Di830_batchbuffer.c183 int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
H A Di915_video.c95 OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
376 OUT_BATCH(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
H A Di810_reg.h2554 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Dintel_batchbuffer.c220 flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
H A Di830_reg.h42 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Dintel_batchbuffer.c220 flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
H A Di830_reg.h42 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h42 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h42 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810_reg.h2546 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810_reg.h2546 #define MI_INVALIDATE_MAP_CACHE (1<<0) macro

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