Searched refs:MT_COMPRESS_DXT1 (Results 1 - 25 of 26) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_state_sampler.c243 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di915_reg.h759 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_state_sampler.c225 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di915_reg.h734 #define MT_COMPRESS_DXT1 (0 << 3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di830_texstate.c71 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di915_texstate.c84 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di830_reg.h572 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h629 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di830_texstate.c71 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di915_texstate.c84 return (MAPSURF_COMPRESSED | MT_COMPRESS_DXT1);
H A Di830_reg.h572 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h629 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen2_render.h660 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Dgen3_render.h744 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di830_reg.h737 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h741 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h731 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h741 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen2_render.h660 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di830_reg.h731 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h741 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h731 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h741 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_reg.h671 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro
H A Di915_reg.h768 #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ macro

Completed in 49 milliseconds

12