Searched refs:ModeReg (Results 1 - 25 of 98) sorted by relevance

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/xsrc/external/mit/xf86-video-cirrus/dist/src/
H A Dlg_driver.c1043 pCir->chip.lg->ModeReg.ExtVga[CR1A] =
1045 pCir->chip.lg->ModeReg.ExtVga[CR1B] =
1047 pCir->chip.lg->ModeReg.ExtVga[CR1D] =
1049 pCir->chip.lg->ModeReg.ExtVga[CR1E] =
1051 pCir->chip.lg->ModeReg.ExtVga[SR07] =
1053 pCir->chip.lg->ModeReg.ExtVga[SR0E] =
1055 pCir->chip.lg->ModeReg.ExtVga[SR1E] =
1058 pCir->chip.lg->ModeReg.FORMAT =
1061 pCir->chip.lg->ModeReg.VSC =
1064 pCir->chip.lg->ModeReg
[all...]
H A Dalp_hwcurs.c32 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg.ExtVga[SR12]|0x02);
41 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg.ExtVga[SR12]);
127 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg.ExtVga[SR12] & ~0x01);
138 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg.ExtVga[SR12]);
156 pAlp->ModeReg.ExtVga[SR13] = 0x3f;
157 hwp->writeSeq(hwp, 0x13, pAlp->ModeReg.ExtVga[SR13]);
169 pAlp->ModeReg.ExtVga[SR12] &= ~0x01;
170 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg.ExtVga[SR12]);
182 pAlp->ModeReg.ExtVga[SR12] |= 0x01;
183 hwp->writeSeq(hwp, 0x12, pAlp->ModeReg
[all...]
H A Dalp_driver.c1135 pCir->chip.alp->ModeReg.ExtVga[CR1A] = pCir->chip.alp->SavedReg.ExtVga[CR1A] = hwp->readCrtc(hwp, 0x1A);
1136 pCir->chip.alp->ModeReg.ExtVga[CR1B] = pCir->chip.alp->SavedReg.ExtVga[CR1B] = hwp->readCrtc(hwp, 0x1B);
1137 pCir->chip.alp->ModeReg.ExtVga[CR1D] = pCir->chip.alp->SavedReg.ExtVga[CR1D] = hwp->readCrtc(hwp, 0x1D);
1138 pCir->chip.alp->ModeReg.ExtVga[SR07] = pCir->chip.alp->SavedReg.ExtVga[SR07] = hwp->readSeq(hwp, 0x07);
1139 pCir->chip.alp->ModeReg.ExtVga[SR0E] = pCir->chip.alp->SavedReg.ExtVga[SR0E] = hwp->readSeq(hwp, 0x0E);
1140 pCir->chip.alp->ModeReg.ExtVga[SR12] = pCir->chip.alp->SavedReg.ExtVga[SR12] = hwp->readSeq(hwp, 0x12);
1141 pCir->chip.alp->ModeReg.ExtVga[SR13] = pCir->chip.alp->SavedReg.ExtVga[SR13] = hwp->readSeq(hwp, 0x13);
1142 pCir->chip.alp->ModeReg.ExtVga[SR17] = pCir->chip.alp->SavedReg.ExtVga[SR17] = hwp->readSeq(hwp, 0x17);
1143 pCir->chip.alp->ModeReg.ExtVga[SR1E] = pCir->chip.alp->SavedReg.ExtVga[SR1E] = hwp->readSeq(hwp, 0x1E);
1144 pCir->chip.alp->ModeReg
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H A Dalp.h58 AlpRegRec ModeReg; member in struct:alpRec
H A Dlg.h96 LgRegRec ModeReg; member in struct:lgRec
/xsrc/external/mit/xf86-video-tdfx/dist/src/
H A Dtdfx_hwcurs.c56 pTDFX->ModeReg.cursloc = pTDFX->cursorOffset;
106 pTDFX->ModeReg.vidcfg|=BIT(27);
107 pTDFX->writeLong(pTDFX, VIDPROCCFG, pTDFX->ModeReg.vidcfg);
117 pTDFX->ModeReg.vidcfg&=~BIT(27);
118 pTDFX->writeLong(pTDFX, VIDPROCCFG, pTDFX->ModeReg.vidcfg);
H A Dtdfx_video.c697 pTDFX->ModeReg.vidcfg &= ~VIDPROCCFGMASK;
698 pTDFX->writeLong(pTDFX, VIDPROCCFG, pTDFX->ModeReg.vidcfg);
715 pTDFX->ModeReg.vidcfg &= ~VIDPROCCFGMASK;
716 pTDFX->writeLong(pTDFX, VIDPROCCFG, pTDFX->ModeReg.vidcfg);
747 The "1" bits are the bits cleared to 0 in pTDFX->ModeReg.vidcfg
809 pTDFX->ModeReg.vidcfg &= ~VIDPROCCFGMASK;
810 pTDFX->ModeReg.vidcfg |= 0x00000320;
812 if(drw_w != src_w) pTDFX->ModeReg.vidcfg |= (1 << 14);
813 if(drw_h != src_h) pTDFX->ModeReg.vidcfg |= (1 << 15);
814 if(id == FOURCC_UYVY) pTDFX->ModeReg
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H A Dtdfx_driver.c1233 pTDFX->ModeReg.miscinit0 = pTDFX->readLong(pTDFX, MISCINIT0);
1234 pTDFX->SavedReg.miscinit0 = pTDFX->ModeReg.miscinit0;
1239 pTDFX->ModeReg.miscinit0 &= ~BIT(30); /* LFB byte swizzle */
1240 pTDFX->ModeReg.miscinit0 &= ~BIT(31); /* LFB word swizzle */
1245 pTDFX->ModeReg.miscinit0 |= BIT(30); /* LFB byte swizzle */
1246 pTDFX->ModeReg.miscinit0 |= BIT(31); /* LFB word swizzle */
1251 pTDFX->ModeReg.miscinit0 |= BIT(30); /* LFB byte swizzle */
1252 pTDFX->ModeReg.miscinit0 &= ~BIT(31); /* LFB word swizzle */
1258 pTDFX->writeLong(pTDFX, MISCINIT0, pTDFX->ModeReg.miscinit0);
1374 vgaRegPtr pVga = &VGAHWPTR(pScrn)->ModeReg;
[all...]
H A Dtdfx_accel.c299 pTDFX->ModeReg.srcbaseaddr=pTDFX->fbOffset;
300 TDFXWriteLongMMIO(pTDFX, SST_2D_SRCBASEADDR, pTDFX->ModeReg.srcbaseaddr);
301 pTDFX->ModeReg.dstbaseaddr=pTDFX->fbOffset;
302 TDFXWriteLongMMIO(pTDFX, SST_2D_DSTBASEADDR, pTDFX->ModeReg.dstbaseaddr);
380 TDFXWriteLong(pTDFX, SST_2D_CLIP1MIN, pTDFX->ModeReg.clip1min);
381 TDFXWriteLong(pTDFX, SST_2D_CLIP1MAX, pTDFX->ModeReg.clip1max);
410 pTDFX->ModeReg.clip1min=(top&0xFFF)<<16 | (left&0xFFF);
411 pTDFX->ModeReg.clip1max=((bottom+1)&0xFFF)<<16 | ((right+1)&0xFFF);
/xsrc/external/mit/xf86-video-mga/dist/src/
H A Dmga_dh.c82 MGARegPtr pReg = &pMga->ModeReg;
183 MGARegPtr pReg = &pMga->ModeReg;
221 pReg = &pMga->ModeReg;
338 pReg = &pMga->ModeReg;
371 pReg = &pMga->ModeReg;
394 pReg = &pMga->ModeReg;
401 pReg = &pMga->ModeReg;
426 pReg = &pMga->ModeReg;
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/vgahw/
H A DvgaCmap.c93 unsigned char overscan = hwp->ModeReg.Attribute[OVERSCAN];
123 cmap = &(hwp->ModeReg.DAC[pdefs[i].pixel*3]);
171 tmp = &(hwp->ModeReg.DAC[pdefs[i].pixel*3]);
183 cmap = &(hwp->ModeReg.DAC[i*3]);
203 hwp->ModeReg.Attribute[OVERSCAN] = overscan;
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_crtc.c893 R128InitCommonRegisters(&info->ModeReg, info);
897 R128InitCrtcRegisters(crtc, &info->ModeReg, adjusted_mode);
898 R128InitCrtcBase(crtc, &info->ModeReg, x, y);
900 R128InitPLLRegisters(crtc, &info->ModeReg, &info->pll, dot_clock);
901 R128InitDDARegisters(crtc, &info->ModeReg, &info->pll, adjusted_mode);
903 info->ModeReg.ppll_ref_div = info->SavedReg.ppll_ref_div;
904 info->ModeReg.ppll_div_3 = info->SavedReg.ppll_div_3;
905 info->ModeReg.htotal_cntl = info->SavedReg.htotal_cntl;
906 info->ModeReg.dda_config = info->SavedReg.dda_config;
907 info->ModeReg
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H A Dr128_output.c130 R128InitRMXRegisters(&info->SavedReg, &info->ModeReg, output, adjusted_mode);
133 R128InitFPRegisters(&info->SavedReg, &info->ModeReg, output);
135 R128InitLVDSRegisters(&info->SavedReg, &info->ModeReg, output);
137 R128InitDACRegisters(&info->SavedReg, &info->ModeReg, output);
140 R128RestoreRMXRegisters(pScrn, &info->ModeReg);
143 R128RestoreFPRegisters(pScrn, &info->ModeReg);
145 R128RestoreLVDSRegisters(pScrn, &info->ModeReg);
147 R128RestoreDACRegisters(pScrn, &info->ModeReg);
218 R128SavePtr save = &info->ModeReg;
258 R128SavePtr save = &info->ModeReg;
[all...]
/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dlegacy_crtc.c661 info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL );
810 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
1032 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the
1802 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
1804 RADEONInitCommonRegisters(info->ModeReg, info);
1806 RADEONInitSurfaceCntl(crtc, info->ModeReg);
1811 RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode);
1812 RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
1816 RADEONInitPLLRegisters(crtc, info->ModeReg, &info->pll, adjusted_mode, pll_flags);
1818 info->ModeReg
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H A Datombios_crtc.c934 RADEONInitCommonRegisters(info->ModeReg, info);
935 RADEONInitSurfaceCntl(crtc, info->ModeReg);
936 RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
962 RADEONInitCrtcBase(crtc, info->ModeReg, x, y);
963 RADEONRestoreCrtcBase(pScrn, info->ModeReg);
970 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y);
971 RADEONRestoreCrtc2Base(pScrn, info->ModeReg);
997 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
998 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/ramdac/
H A Dxf86RamDac.h26 RamDacRegRec ModeReg; member in struct:_RamDacHWRegRec
/xsrc/external/mit/xf86-video-nv/dist/src/
H A Driva_dac.c51 RivaRegPtr rivaReg = &pRiva->ModeReg;
61 pVga = &VGAHWPTR(pScrn)->ModeReg;
201 pVga = &VGAHWPTR(pScrn)->ModeReg;
H A Dnv_dac.c89 NVRegPtr nvReg = &pNv->ModeReg;
101 pVga = &VGAHWPTR(pScrn)->ModeReg;
331 pVga = &VGAHWPTR(pScrn)->ModeReg;
/xsrc/external/mit/xf86-video-i740/dist/src/
H A Di740.h115 I740RegRec ModeReg; member in struct:_I740Rec
/xsrc/external/mit/xf86-video-vmware/dist/src/
H A Dvmwarectrl.c301 if (maxX == pVMWARE->ModeReg.svga_reg_width &&
302 maxY == pVMWARE->ModeReg.svga_reg_height) {
H A Dvmware.c223 BB.x2 = pVMWARE->ModeReg.svga_reg_width;
224 BB.y2 = pVMWARE->ModeReg.svga_reg_height;
872 vgaRegPtr vgaReg = &hwp->ModeReg;
874 VMWARERegPtr vmwareReg = &pVMWARE->ModeReg;
943 VMWARERegPtr vmwareReg = &pVMWARE->ModeReg;
1202 if (boxPtr->y2 >= pVMWARE->ModeReg.svga_reg_height)
1203 boxPtr->y2 = pVMWARE->ModeReg.svga_reg_height;
1204 if (boxPtr->y1 >= pVMWARE->ModeReg.svga_reg_height)
1205 boxPtr->y1 = pVMWARE->ModeReg.svga_reg_height;
/xsrc/external/mit/xf86-video-xgi/dist/src/
H A Dxgi_vga.c65 XGIRegPtr pReg = &pXGI->ModeReg;
66 vgaRegPtr vgaReg = &VGAHWPTR(pScrn)->ModeReg;
/xsrc/external/mit/xf86-video-intel/dist/src/legacy/i810/
H A Di810.h205 I810RegRec ModeReg; member in struct:_I810Rec
266 #define I810REGPTR(p) (&(I810PTR(p)->ModeReg))
/xsrc/external/mit/xf86-video-intel-2014/dist/src/legacy/i810/
H A Di810.h205 I810RegRec ModeReg; member in struct:_I810Rec
267 #define I810REGPTR(p) (&(I810PTR(p)->ModeReg))
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di810.h219 I810RegRec ModeReg; member in struct:_I810Rec
286 #define I810REGPTR(p) (&(I810PTR(p)->ModeReg))

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