Searched refs:NV50_3D (Results 1 - 25 of 34) sorted by relevance

12

/xsrc/external/mit/xf86-video-nouveau/dist/src/
H A Dnv50_accel.h22 #define NV50_3D(mthd) SUBC_3D(NV50_3D_##mthd) macro
53 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(8)), 2);
56 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2I(0)), 1);
64 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2I(8)), 2);
67 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2I(0)), 1);
77 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
81 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
83 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), dwords);
H A Dnv50_accel.c193 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
195 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
197 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
200 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
203 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
206 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
208 BEGIN_NV04(push, NV50_3D(COLOR_MASK_COMMON), 1);
210 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
213 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3);
217 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIG
[all...]
H A Dnv50_xv.c92 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
104 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
107 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
110 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
208 BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
211 BEGIN_NV04(push, NV50_3D(TIC_FLUSH), 1);
214 BEGIN_NV04(push, NV50_3D(BIND_TIC(2)), 1);
216 BEGIN_NV04(push, NV50_3D(BIND_TIC(2)), 1);
261 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
264 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_G
[all...]
H A Dnv50_exa.c449 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
455 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
458 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
787 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
790 BEGIN_NV04(push, NV50_3D(BLEND_ENABLE(0)), 1);
792 BEGIN_NV04(push, NV50_3D(BLEND_EQUATION_RGB), 5);
798 BEGIN_NV04(push, NV50_3D(BLEND_FUNC_DST_ALPHA), 1);
858 BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
873 BEGIN_NV04(push, NV50_3D(FP_START_ID), 1);
880 BEGIN_NV04(push, NV50_3D(TIC_FLUS
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_screen.c645 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
700 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
703 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
705 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
708 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
712 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
714 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
718 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
722 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
725 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABL
[all...]
H A Dnv50_shader_state.c67 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
74 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
76 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
91 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
96 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
104 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
164 BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
167 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
169 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
171 BEGIN_NV04(push, NV50_3D(VP_START_I
[all...]
H A Dnv50_vbo.c156 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
163 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
169 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
175 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
178 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
268 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
271 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
323 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
331 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
356 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANC
[all...]
H A Dnv50_state_validate.c9 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 4);
14 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
30 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
32 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
57 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
66 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
69 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
75 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
78 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
101 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIG
[all...]
H A Dnv50_surface.c292 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
303 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
306 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
311 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
313 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
319 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
325 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
331 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
335 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
341 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORI
[all...]
H A Dnv50_push.c87 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
100 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
126 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
139 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
165 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
178 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
199 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
318 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 2);
323 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 1);
329 BEGIN_NV04(ctx.push, NV50_3D(VERTEX_BEGIN_G
[all...]
H A Dnv50_tex.c259 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
301 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
315 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
323 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
330 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
335 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
364 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1);
389 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
407 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
414 BEGIN_NV04(push, NV50_3D(BIND_TS
[all...]
H A Dnv50_stateobj.h10 (so)->state[(so)->size++] = NV50_FIFO_PKHDR(NV50_3D(m), s)
H A Dnv50_query_hw.c86 BEGIN_NV04(push, NV50_3D(QUERY_ADDRESS_HIGH), 4);
159 BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1);
161 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
217 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
H A Dnv50_winsys.h51 #define NV50_3D(n) SUBC_3D(NV50_3D_##n) macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_screen.c569 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
624 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
627 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1);
629 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11);
632 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN);
636 BEGIN_NV04(push, NV50_3D(REG_MODE), 1);
638 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1);
642 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1);
646 BEGIN_NV04(push, NV50_3D(ZETA_COMP_ENABLE), 1);
649 BEGIN_NV04(push, NV50_3D(RT_COMP_ENABL
[all...]
H A Dnv50_shader_state.c67 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
74 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
76 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nr);
91 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
96 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
104 BEGIN_NV04(push, NV50_3D(SET_PROGRAM_CB), 1);
159 BEGIN_NV04(push, NV50_3D(VP_ATTR_EN(0)), 2);
162 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_RESULT), 1);
164 BEGIN_NV04(push, NV50_3D(VP_REG_ALLOC_TEMP), 1);
166 BEGIN_NV04(push, NV50_3D(VP_START_I
[all...]
H A Dnv50_vbo.c164 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4);
171 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3);
177 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2);
183 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1);
186 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1);
275 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2);
278 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2);
330 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n);
338 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1);
363 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANC
[all...]
H A Dnv50_state_validate.c9 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 4);
14 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
30 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
32 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
57 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
66 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
69 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
75 BEGIN_NV04(push, NV50_3D(RT_HORIZ(i)), 2);
78 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
101 BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIG
[all...]
H A Dnv50_surface.c292 BEGIN_NV04(push, NV50_3D(CLEAR_COLOR(0)), 4);
303 BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
306 BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
311 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
313 BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
319 BEGIN_NV04(push, NV50_3D(RT_HORIZ(0)), 2);
325 BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
331 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1);
335 BEGIN_NV04(push, NV50_3D(ZETA_ENABLE), 1);
341 BEGIN_NV04(push, NV50_3D(VIEWPORT_HORI
[all...]
H A Dnv50_push.c87 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
100 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
126 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
139 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
165 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
178 BEGIN_NV04(ctx->push, NV50_3D(VB_ELEMENT_U32), 1);
199 BEGIN_NI04(ctx->push, NV50_3D(VERTEX_DATA), size);
316 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 2);
321 BEGIN_NV04(ctx.push, NV50_3D(PRIM_RESTART_ENABLE), 1);
327 BEGIN_NV04(ctx.push, NV50_3D(VERTEX_BEGIN_G
[all...]
H A Dnv50_tex.c253 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
292 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
303 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
307 BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
311 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
313 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
342 BEGIN_NV04(nv50->base.pushbuf, NV50_3D(TIC_FLUSH), 1);
359 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
374 BEGIN_NV04(push, NV50_3D(BIND_TSC(s)), 1);
378 BEGIN_NV04(push, NV50_3D(BIND_TS
[all...]
H A Dnv50_stateobj.h10 (so)->state[(so)->size++] = NV50_FIFO_PKHDR(NV50_3D(m), s)
H A Dnv50_query_hw.c86 BEGIN_NV04(push, NV50_3D(QUERY_ADDRESS_HIGH), 4);
160 BEGIN_NV04(push, NV50_3D(COUNTER_RESET), 1);
162 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
217 BEGIN_NV04(push, NV50_3D(SAMPLECNT_ENABLE), 1);
H A Dnv50_winsys.h51 #define NV50_3D(n) SUBC_3D(NV50_3D_##n) macro
H A Dnv50_query.c123 BEGIN_NV04(push, NV50_3D(COND_MODE), 1);
136 BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);

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