Searched refs:NV_VRAM_DOMAIN (Results 1 - 25 of 28) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/
H A Dnouveau_screen.h111 #define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain) macro
H A Dnouveau_buffer.c660 buffer->domain = NV_VRAM_DOMAIN(screen);
666 buffer->domain = NV_VRAM_DOMAIN(screen);
678 buffer->domain = NV_VRAM_DOMAIN(screen);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/
H A Dnouveau_screen.h118 #define NV_VRAM_DOMAIN(screen) ((screen)->vram_domain) macro
H A Dnouveau_buffer.c702 buffer->domain = NV_VRAM_DOMAIN(screen);
708 buffer->domain = NV_VRAM_DOMAIN(screen);
720 buffer->domain = NV_VRAM_DOMAIN(screen);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_screen.c807 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
817 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
830 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
840 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
1245 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1250 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1300 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1311 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
H A Dnvc0_tex.c472 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
506 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
572 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
647 65536 + tsc->id * 32, NV_VRAM_DOMAIN(&nvc0->screen->base),
703 NV_VRAM_DOMAIN(&nvc0->screen->base),
751 NV_VRAM_DOMAIN(&nvc0->screen->base), 32, data);
817 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
825 NV_VRAM_DOMAIN(&nvc0->screen->base),
1255 NV_VRAM_DOMAIN(&nvc0->screen->base), 32, tic->tic);
1429 NV_VRAM_DOMAIN(
[all...]
H A Dnvc0_compute.c216 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
468 PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
H A Dnvc0_context.c453 flags = NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD;
462 flags = NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR;
H A Dnvc0_program.c808 NV_VRAM_DOMAIN(&screen->base),
812 NV_VRAM_DOMAIN(&screen->base), prog->code_size,
920 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
H A Dnvc0_miptree.c382 mt->base.domain = NV_VRAM_DOMAIN(nouveau_screen(pscreen));
H A Dnvc0_shader_state.c38 const uint32_t flags = NV_VRAM_DOMAIN(&nvc0->screen->base) | NOUVEAU_BO_RDWR;
H A Dnvc0_state_validate.c590 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
839 NV_VRAM_DOMAIN(&screen->base), 32, tic->tic);
H A Dnvc0_vbo.c922 unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base);
H A Dnve4_compute.c783 PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_screen.c916 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
926 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR);
939 ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
949 NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
1305 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 13 << 16, NULL,
1310 PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
1360 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
1371 ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
H A Dnvc0_tex.c470 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
504 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
570 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
645 65536 + tsc->id * 32, NV_VRAM_DOMAIN(&nvc0->screen->base),
701 NV_VRAM_DOMAIN(&nvc0->screen->base),
749 NV_VRAM_DOMAIN(&nvc0->screen->base), 32, data);
815 NV_VRAM_DOMAIN(&nvc0->screen->base), 32,
823 NV_VRAM_DOMAIN(&nvc0->screen->base),
1268 NV_VRAM_DOMAIN(&nvc0->screen->base), 32, tic->tic);
1442 NV_VRAM_DOMAIN(
[all...]
H A Dnvc0_compute.c216 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
468 PUSH_REFN(push, screen->text, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD);
H A Dnvc0_context.c509 flags = NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD;
518 flags = NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RDWR;
H A Dnvc0_program.c865 NV_VRAM_DOMAIN(&screen->base), size_sph, prog->hdr);
868 NV_VRAM_DOMAIN(&screen->base), prog->code_size,
982 screen->text, screen->lib_code->start, NV_VRAM_DOMAIN(&screen->base),
H A Dnvc0_shader_state.c38 const uint32_t flags = NV_VRAM_DOMAIN(&nvc0->screen->base) | NOUVEAU_BO_RDWR;
H A Dnvc0_miptree.c531 mt->base.domain = NV_VRAM_DOMAIN(nouveau_screen(pscreen));
H A Dnvc0_state_validate.c599 nvc0_cb_bo_push(&nvc0->base, bo, NV_VRAM_DOMAIN(&nvc0->screen->base),
848 NV_VRAM_DOMAIN(&screen->base), 32, tic->tic);
H A Dnvc0_vbo.c944 unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_miptree.c383 mt->base.domain = NV_VRAM_DOMAIN(nouveau_screen(pscreen));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nv50/
H A Dnv50_miptree.c386 mt->base.domain = NV_VRAM_DOMAIN(nouveau_screen(pscreen));

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