| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 97 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
217 case OP_INSBF:
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| H A D | nv50_ir_lowering_nvc0.cpp | 1004 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
1089 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
1091 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
1125 bld.mkOp3(OP_INSBF, TYPE_U32,
1153 bld.mkOp3(OP_INSBF, TYPE_U32, offset,
2641 ptr = bld.mkOp3v(OP_INSBF, TYPE_U32, bld.getSSA(),
3011 bld.mkOp3(OP_INSBF, TYPE_U32, offset, sampleID, bld.mkImm(0x0302), bld.mkImm(0x0));
3022 bld.mkOp3(OP_INSBF, TYPE_U32, offset, coord, bld.mkImm(0x0105), offset);
3029 bld.mkOp3(OP_INSBF, TYPE_U32, offset, coord, bld.mkImm(0x0206), offset);
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| H A D | nv50_ir_target_nv50.cpp | 441 case OP_INSBF:
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| H A D | nv50_ir_from_nir.cpp | 2081 mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[1], mkImm(0x1010), offs[0]);
2919 mkOp3(OP_INSBF, TYPE_U32, newDefs[0], tmpH, mkImm(0x1010), tmpL);
2986 mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2993 mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
3000 mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
3001 mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
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| H A D | nv50_ir.h | 151 OP_INSBF, // insert first src1[8:15] bits of src0 into src2 at src1[0:7] enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_target_nvc0.cpp | 137 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
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| H A D | nv50_ir_from_tgsi.cpp | 3103 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
3544 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3827 mkOp3(OP_INSBF, TYPE_U32, val0, src2, mkImm(0x808), src1);
3839 mkOp3(OP_INSBF, TYPE_U32, val0, src3, mkImm(0x808), src2);
3840 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, val0, src0);
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| H A D | nv50_ir_emit_gk110.cpp | 2696 case OP_INSBF:
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| H A D | nv50_ir_emit_nv50.cpp | 2054 case OP_INSBF:
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| H A D | nv50_ir_emit_gm107.cpp | 3504 case OP_INSBF:
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| H A D | nv50_ir_emit_nvc0.cpp | 2890 case OP_INSBF:
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| H A D | nv50_ir_peephole.cpp | 783 case OP_INSBF: {
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 97 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
217 case OP_INSBF:
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| H A D | nv50_ir_lowering_nvc0.cpp | 1018 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
1103 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
1105 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
1139 bld.mkOp3(OP_INSBF, TYPE_U32,
1167 bld.mkOp3(OP_INSBF, TYPE_U32, offset,
2855 ptr = bld.mkOp3v(OP_INSBF, TYPE_U32, bld.getSSA(),
3225 bld.mkOp3(OP_INSBF, TYPE_U32, offset, sampleID, bld.mkImm(0x0302), bld.mkImm(0x0));
3236 bld.mkOp3(OP_INSBF, TYPE_U32, offset, coord, bld.mkImm(0x0105), offset);
3243 bld.mkOp3(OP_INSBF, TYPE_U32, offset, coord, bld.mkImm(0x0206), offset);
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| H A D | nv50_ir_lowering_gv100.cpp | 460 case OP_INSBF:
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| H A D | nv50_ir_target_nv50.cpp | 452 case OP_INSBF:
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| H A D | nv50_ir_from_nir.cpp | 1811 mkOp3v(OP_INSBF, TYPE_U32, newDefs[0], offs[1], mkImm(0x1010), offs[0]);
2641 mkOp3(OP_INSBF, TYPE_U32, newDefs[0], tmpH, mkImm(0x1010), tmpL);
2708 mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1]));
2722 mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2]));
2723 mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0]));
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| H A D | nv50_ir.h | 154 OP_INSBF, // insert first src1[8:15] bits of src0 into src2 at src1[0:7] enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_target_nvc0.cpp | 137 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
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| H A D | nv50_ir_from_tgsi.cpp | 3126 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
3576 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3861 mkOp3(OP_INSBF, TYPE_U32, val0, src2, mkImm(0x808), src1);
3873 mkOp3(OP_INSBF, TYPE_U32, val0, src3, mkImm(0x808), src2);
3874 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, val0, src0);
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| H A D | nv50_ir_emit_gk110.cpp | 2703 case OP_INSBF:
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| H A D | nv50_ir_emit_nv50.cpp | 2141 case OP_INSBF:
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| H A D | nv50_ir_emit_gm107.cpp | 3569 case OP_INSBF:
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| H A D | nv50_ir_emit_nvc0.cpp | 2897 case OP_INSBF:
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| H A D | nv50_ir_peephole.cpp | 816 case OP_INSBF: {
|